1/* 2 * Startup Code for MIPS32 CPU-core 3 * 4 * Copyright (c) 2003 Wolfgang Denk <wd@denx.de> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9#include <asm-offsets.h> 10#include <config.h> 11#include <asm/asm.h> 12#include <asm/regdef.h> 13#include <asm/mipsregs.h> 14 15#ifndef CONFIG_SYS_INIT_SP_ADDR 16#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \ 17 CONFIG_SYS_INIT_SP_OFFSET) 18#endif 19 20#ifdef CONFIG_32BIT 21# define MIPS_RELOC 3 22# define STATUS_SET 0 23#endif 24 25#ifdef CONFIG_64BIT 26# ifdef CONFIG_SYS_LITTLE_ENDIAN 27# define MIPS64_R_INFO(ssym, r_type3, r_type2, r_type) \ 28 (((r_type) << 24) | ((r_type2) << 16) | ((r_type3) << 8) | (ssym)) 29# else 30# define MIPS64_R_INFO(ssym, r_type3, r_type2, r_type) \ 31 ((r_type) | ((r_type2) << 8) | ((r_type3) << 16) | (ssym) << 24) 32# endif 33# define MIPS_RELOC MIPS64_R_INFO(0x00, 0x00, 0x12, 0x03) 34# define STATUS_SET ST0_KX 35#endif 36 37 /* 38 * For the moment disable interrupts, mark the kernel mode and 39 * set ST0_KX so that the CPU does not spit fire when using 40 * 64-bit addresses. 41 */ 42 .macro setup_c0_status set clr 43 .set push 44 mfc0 t0, CP0_STATUS 45 or t0, ST0_CU0 | \set | 0x1f | \clr 46 xor t0, 0x1f | \clr 47 mtc0 t0, CP0_STATUS 48 .set noreorder 49 sll zero, 3 # ehb 50 .set pop 51 .endm 52 53 .set noreorder 54 55ENTRY(_start) 56 /* U-Boot entry point */ 57 b reset 58 nop 59 60 .org 0x10 61#if defined(CONFIG_SYS_XWAY_EBU_BOOTCFG) 62 /* 63 * Almost all Lantiq XWAY SoC devices have an external bus unit (EBU) to 64 * access external NOR flashes. If the board boots from NOR flash the 65 * internal BootROM does a blind read at address 0xB0000010 to read the 66 * initial configuration for that EBU in order to access the flash 67 * device with correct parameters. This config option is board-specific. 68 */ 69 .word CONFIG_SYS_XWAY_EBU_BOOTCFG 70 .word 0x0 71#elif defined(CONFIG_MALTA) 72 /* 73 * Linux expects the Board ID here. 74 */ 75 .word 0x00000420 # 0x420 (Malta Board with CoreLV) 76 .word 0x00000000 77#endif 78 79 .org 0x200 80 /* TLB refill, 32 bit task */ 811: b 1b 82 nop 83 84 .org 0x280 85 /* XTLB refill, 64 bit task */ 861: b 1b 87 nop 88 89 .org 0x300 90 /* Cache error exception */ 911: b 1b 92 nop 93 94 .org 0x380 95 /* General exception */ 961: b 1b 97 nop 98 99 .org 0x400 100 /* Catch interrupt exceptions */ 1011: b 1b 102 nop 103 104 .org 0x480 105 /* EJTAG debug exception */ 1061: b 1b 107 nop 108 109 .align 4 110reset: 111 112 /* Clear watch registers */ 113 MTC0 zero, CP0_WATCHLO 114 mtc0 zero, CP0_WATCHHI 115 116 /* WP(Watch Pending), SW0/1 should be cleared */ 117 mtc0 zero, CP0_CAUSE 118 119 setup_c0_status STATUS_SET 0 120 121 /* Init Timer */ 122 mtc0 zero, CP0_COUNT 123 mtc0 zero, CP0_COMPARE 124 125#ifndef CONFIG_SKIP_LOWLEVEL_INIT 126 mfc0 t0, CP0_CONFIG 127 and t0, t0, MIPS_CONF_IMPL 128 or t0, t0, CONF_CM_UNCACHED 129 mtc0 t0, CP0_CONFIG 130#endif 131 132 /* 133 * Initialize $gp, force pointer sized alignment of bal instruction to 134 * forbid the compiler to put nop's between bal and _gp. This is 135 * required to keep _gp and ra aligned to 8 byte. 136 */ 137 .align PTRLOG 138 bal 1f 139 nop 140 PTR _gp 1411: 142 PTR_L gp, 0(ra) 143 144#ifndef CONFIG_SKIP_LOWLEVEL_INIT 145 /* Initialize any external memory */ 146 PTR_LA t9, lowlevel_init 147 jalr t9 148 nop 149 150 /* Initialize caches... */ 151 PTR_LA t9, mips_cache_reset 152 jalr t9 153 nop 154#endif 155 156 /* Set up temporary stack */ 157 li t0, -16 158 PTR_LI t1, CONFIG_SYS_INIT_SP_ADDR 159 and sp, t1, t0 # force 16 byte alignment 160 PTR_SUBU \ 161 sp, sp, GD_SIZE # reserve space for gd 162 and sp, sp, t0 # force 16 byte alignment 163 move k0, sp # save gd pointer 164#ifdef CONFIG_SYS_MALLOC_F_LEN 165 li t2, CONFIG_SYS_MALLOC_F_LEN 166 PTR_SUBU \ 167 sp, sp, t2 # reserve space for early malloc 168 and sp, sp, t0 # force 16 byte alignment 169#endif 170 move fp, sp 171 172 /* Clear gd */ 173 move t0, k0 1741: 175 PTR_S zero, 0(t0) 176 blt t0, t1, 1b 177 PTR_ADDIU t0, PTRSIZE 178 179#ifdef CONFIG_SYS_MALLOC_F_LEN 180 PTR_S sp, GD_MALLOC_BASE(k0) # gd->malloc_base offset 181#endif 182 183 move a0, zero # a0 <-- boot_flags = 0 184 PTR_LA t9, board_init_f 185 jr t9 186 move ra, zero 187 188 END(_start) 189 190/* 191 * void relocate_code (addr_sp, gd, addr_moni) 192 * 193 * This "function" does not return, instead it continues in RAM 194 * after relocating the monitor code. 195 * 196 * a0 = addr_sp 197 * a1 = gd 198 * a2 = destination address 199 */ 200ENTRY(relocate_code) 201 move sp, a0 # set new stack pointer 202 move fp, sp 203 204 move s0, a1 # save gd in s0 205 move s2, a2 # save destination address in s2 206 207 PTR_LI t0, CONFIG_SYS_MONITOR_BASE 208 PTR_SUB s1, s2, t0 # s1 <-- relocation offset 209 210 PTR_LA t3, in_ram 211 PTR_L t2, -(3 * PTRSIZE)(t3) # t2 <-- __image_copy_end 212 move t1, a2 213 214 PTR_ADD gp, s1 # adjust gp 215 216 /* 217 * t0 = source address 218 * t1 = target address 219 * t2 = source end address 220 */ 2211: 222 PTR_L t3, 0(t0) 223 PTR_S t3, 0(t1) 224 PTR_ADDU t0, PTRSIZE 225 blt t0, t2, 1b 226 PTR_ADDU t1, PTRSIZE 227 228 /* If caches were enabled, we would have to flush them here. */ 229 PTR_SUB a1, t1, s2 # a1 <-- size 230 PTR_LA t9, flush_cache 231 jalr t9 232 move a0, s2 # a0 <-- destination address 233 234 /* Jump to where we've relocated ourselves */ 235 PTR_ADDIU t0, s2, in_ram - _start 236 jr t0 237 nop 238 239 PTR __rel_dyn_end 240 PTR __rel_dyn_start 241 PTR __image_copy_end 242 PTR _GLOBAL_OFFSET_TABLE_ 243 PTR num_got_entries 244 245in_ram: 246 /* 247 * Now we want to update GOT. 248 * 249 * GOT[0] is reserved. GOT[1] is also reserved for the dynamic object 250 * generated by GNU ld. Skip these reserved entries from relocation. 251 */ 252 PTR_L t3, -(1 * PTRSIZE)(t0) # t3 <-- num_got_entries 253 PTR_L t8, -(2 * PTRSIZE)(t0) # t8 <-- _GLOBAL_OFFSET_TABLE_ 254 PTR_ADD t8, s1 # t8 now holds relocated _G_O_T_ 255 PTR_ADDIU t8, t8, 2 * PTRSIZE # skipping first two entries 256 PTR_LI t2, 2 2571: 258 PTR_L t1, 0(t8) 259 beqz t1, 2f 260 PTR_ADD t1, s1 261 PTR_S t1, 0(t8) 2622: 263 PTR_ADDIU t2, 1 264 blt t2, t3, 1b 265 PTR_ADDIU t8, PTRSIZE 266 267 /* Update dynamic relocations */ 268 PTR_L t1, -(4 * PTRSIZE)(t0) # t1 <-- __rel_dyn_start 269 PTR_L t2, -(5 * PTRSIZE)(t0) # t2 <-- __rel_dyn_end 270 271 b 2f # skip first reserved entry 272 PTR_ADDIU t1, 2 * PTRSIZE 273 2741: 275 lw t8, -4(t1) # t8 <-- relocation info 276 277 PTR_LI t3, MIPS_RELOC 278 bne t8, t3, 2f # skip non-MIPS_RELOC entries 279 nop 280 281 PTR_L t3, -(2 * PTRSIZE)(t1) # t3 <-- location to fix up in FLASH 282 283 PTR_L t8, 0(t3) # t8 <-- original pointer 284 PTR_ADD t8, s1 # t8 <-- adjusted pointer 285 286 PTR_ADD t3, s1 # t3 <-- location to fix up in RAM 287 PTR_S t8, 0(t3) 288 2892: 290 blt t1, t2, 1b 291 PTR_ADDIU t1, 2 * PTRSIZE # each rel.dyn entry is 2*PTRSIZE bytes 292 293 /* 294 * Clear BSS 295 * 296 * GOT is now relocated. Thus __bss_start and __bss_end can be 297 * accessed directly via $gp. 298 */ 299 PTR_LA t1, __bss_start # t1 <-- __bss_start 300 PTR_LA t2, __bss_end # t2 <-- __bss_end 301 3021: 303 PTR_S zero, 0(t1) 304 blt t1, t2, 1b 305 PTR_ADDIU t1, PTRSIZE 306 307 move a0, s0 # a0 <-- gd 308 move a1, s2 309 PTR_LA t9, board_init_r 310 jr t9 311 move ra, zero 312 313 END(relocate_code) 314