xref: /rk3399_rockchip-uboot/arch/mips/cpu/start.S (revision d263cda5ae41279208d9576eab1c5215a57252a6) 
1/*
2 *  Startup Code for MIPS32 CPU-core
3 *
4 *  Copyright (c) 2003	Wolfgang Denk <wd@denx.de>
5 *
6 * SPDX-License-Identifier:	GPL-2.0+
7 */
8
9#include <asm-offsets.h>
10#include <config.h>
11#include <asm/asm.h>
12#include <asm/regdef.h>
13#include <asm/mipsregs.h>
14
15#ifndef CONFIG_SYS_INIT_SP_ADDR
16#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_SDRAM_BASE + \
17				CONFIG_SYS_INIT_SP_OFFSET)
18#endif
19
20#ifdef CONFIG_32BIT
21# define MIPS_RELOC	3
22# define STATUS_SET	0
23#endif
24
25#ifdef CONFIG_64BIT
26# ifdef CONFIG_SYS_LITTLE_ENDIAN
27#  define MIPS64_R_INFO(ssym, r_type3, r_type2, r_type) \
28	(((r_type) << 24) | ((r_type2) << 16) | ((r_type3) << 8) | (ssym))
29# else
30#  define MIPS64_R_INFO(ssym, r_type3, r_type2, r_type) \
31	((r_type) | ((r_type2) << 8) | ((r_type3) << 16) | (ssym) << 24)
32# endif
33# define MIPS_RELOC	MIPS64_R_INFO(0x00, 0x00, 0x12, 0x03)
34# define STATUS_SET	ST0_KX
35#endif
36
37	/*
38	 * For the moment disable interrupts, mark the kernel mode and
39	 * set ST0_KX so that the CPU does not spit fire when using
40	 * 64-bit addresses.
41	 */
42	.macro	setup_c0_status set clr
43	.set	push
44	mfc0	t0, CP0_STATUS
45	or	t0, ST0_CU0 | \set | 0x1f | \clr
46	xor	t0, 0x1f | \clr
47	mtc0	t0, CP0_STATUS
48	.set	noreorder
49	sll	zero, 3				# ehb
50	.set	pop
51	.endm
52
53	.set noreorder
54
55ENTRY(_start)
56	/* U-Boot entry point */
57	b	reset
58	 nop
59
60	.org 0x10
61#if defined(CONFIG_SYS_XWAY_EBU_BOOTCFG)
62	/*
63	 * Almost all Lantiq XWAY SoC devices have an external bus unit (EBU) to
64	 * access external NOR flashes. If the board boots from NOR flash the
65	 * internal BootROM does a blind read at address 0xB0000010 to read the
66	 * initial configuration for that EBU in order to access the flash
67	 * device with correct parameters. This config option is board-specific.
68	 */
69	.word CONFIG_SYS_XWAY_EBU_BOOTCFG
70	.word 0x0
71#elif defined(CONFIG_MALTA)
72	/*
73	 * Linux expects the Board ID here.
74	 */
75	.word 0x00000420	# 0x420 (Malta Board with CoreLV)
76	.word 0x00000000
77#endif
78
79	.org 0x200
80	/* TLB refill, 32 bit task */
811:	b	1b
82	 nop
83
84	.org 0x280
85	/* XTLB refill, 64 bit task */
861:	b	1b
87	 nop
88
89	.org 0x300
90	/* Cache error exception */
911:	b	1b
92	 nop
93
94	.org 0x380
95	/* General exception */
961:	b	1b
97	 nop
98
99	.org 0x400
100	/* Catch interrupt exceptions */
1011:	b	1b
102	 nop
103
104	.org 0x480
105	/* EJTAG debug exception */
1061:	b	1b
107	 nop
108
109	.align 4
110reset:
111
112	/* Clear watch registers */
113	MTC0	zero, CP0_WATCHLO
114	mtc0	zero, CP0_WATCHHI
115
116	/* WP(Watch Pending), SW0/1 should be cleared */
117	mtc0	zero, CP0_CAUSE
118
119	setup_c0_status STATUS_SET 0
120
121	/* Init Timer */
122	mtc0	zero, CP0_COUNT
123	mtc0	zero, CP0_COMPARE
124
125#ifndef CONFIG_SKIP_LOWLEVEL_INIT
126	mfc0	t0, CP0_CONFIG
127	and	t0, t0, MIPS_CONF_IMPL
128	or	t0, t0, CONF_CM_UNCACHED
129	mtc0	t0, CP0_CONFIG
130	ehb
131#endif
132
133	/*
134	 * Initialize $gp, force pointer sized alignment of bal instruction to
135	 * forbid the compiler to put nop's between bal and _gp. This is
136	 * required to keep _gp and ra aligned to 8 byte.
137	 */
138	.align	PTRLOG
139	bal	1f
140	 nop
141	PTR	_gp
1421:
143	PTR_L	gp, 0(ra)
144
145#ifdef CONFIG_MIPS_CM
146	PTR_LA	t9, mips_cm_map
147	jalr	t9
148	 nop
149#endif
150
151#ifndef CONFIG_SKIP_LOWLEVEL_INIT
152# ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
153	/* Initialize any external memory */
154	PTR_LA	t9, lowlevel_init
155	jalr	t9
156	 nop
157# endif
158
159	/* Initialize caches... */
160	PTR_LA	t9, mips_cache_reset
161	jalr	t9
162	 nop
163
164# ifndef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
165	/* Initialize any external memory */
166	PTR_LA	t9, lowlevel_init
167	jalr	t9
168	 nop
169# endif
170#endif
171
172	/* Set up temporary stack */
173	li	t0, -16
174	PTR_LI	t1, CONFIG_SYS_INIT_SP_ADDR
175	and	sp, t1, t0		# force 16 byte alignment
176	PTR_SUBU \
177		sp, sp, GD_SIZE		# reserve space for gd
178	and	sp, sp, t0		# force 16 byte alignment
179	move	k0, sp			# save gd pointer
180#ifdef CONFIG_SYS_MALLOC_F_LEN
181	li	t2, CONFIG_SYS_MALLOC_F_LEN
182	PTR_SUBU \
183		sp, sp, t2		# reserve space for early malloc
184	and	sp, sp, t0		# force 16 byte alignment
185#endif
186	move	fp, sp
187
188	/* Clear gd */
189	move	t0, k0
1901:
191	PTR_S	zero, 0(t0)
192	blt	t0, t1, 1b
193	 PTR_ADDIU t0, PTRSIZE
194
195#ifdef CONFIG_SYS_MALLOC_F_LEN
196	PTR_S	sp, GD_MALLOC_BASE(k0)	# gd->malloc_base offset
197#endif
198
199	move	a0, zero		# a0 <-- boot_flags = 0
200	PTR_LA	t9, board_init_f
201	jr	t9
202	 move	ra, zero
203
204	END(_start)
205
206/*
207 * void relocate_code (addr_sp, gd, addr_moni)
208 *
209 * This "function" does not return, instead it continues in RAM
210 * after relocating the monitor code.
211 *
212 * a0 = addr_sp
213 * a1 = gd
214 * a2 = destination address
215 */
216ENTRY(relocate_code)
217	move	sp, a0			# set new stack pointer
218	move	fp, sp
219
220	move	s0, a1			# save gd in s0
221	move	s2, a2			# save destination address in s2
222
223	PTR_LI	t0, CONFIG_SYS_MONITOR_BASE
224	PTR_SUB	s1, s2, t0		# s1 <-- relocation offset
225
226	PTR_LA	t2, __image_copy_end
227	move	t1, a2
228
229	/*
230	 * t0 = source address
231	 * t1 = target address
232	 * t2 = source end address
233	 */
2341:
235	PTR_L	t3, 0(t0)
236	PTR_S	t3, 0(t1)
237	PTR_ADDU t0, PTRSIZE
238	blt	t0, t2, 1b
239	 PTR_ADDU t1, PTRSIZE
240
241	/*
242	 * Now we want to update GOT.
243	 *
244	 * GOT[0] is reserved. GOT[1] is also reserved for the dynamic object
245	 * generated by GNU ld. Skip these reserved entries from relocation.
246	 */
247	PTR_LA	t3, num_got_entries
248	PTR_LA	t8, _GLOBAL_OFFSET_TABLE_
249	PTR_ADD	t8, s1			# t8 now holds relocated _G_O_T_
250	PTR_ADDIU t8, t8, 2 * PTRSIZE	# skipping first two entries
251	PTR_LI	t2, 2
2521:
253	PTR_L	t1, 0(t8)
254	beqz	t1, 2f
255	 PTR_ADD t1, s1
256	PTR_S	t1, 0(t8)
2572:
258	PTR_ADDIU t2, 1
259	blt	t2, t3, 1b
260	 PTR_ADDIU t8, PTRSIZE
261
262	/* Update dynamic relocations */
263	PTR_LA	t1, __rel_dyn_start
264	PTR_LA	t2, __rel_dyn_end
265
266	b	2f			# skip first reserved entry
267	 PTR_ADDIU t1, 2 * PTRSIZE
268
2691:
270	lw	t8, -4(t1)		# t8 <-- relocation info
271
272	PTR_LI	t3, MIPS_RELOC
273	bne	t8, t3, 2f		# skip non-MIPS_RELOC entries
274	 nop
275
276	PTR_L	t3, -(2 * PTRSIZE)(t1)	# t3 <-- location to fix up in FLASH
277
278	PTR_L	t8, 0(t3)		# t8 <-- original pointer
279	PTR_ADD	t8, s1			# t8 <-- adjusted pointer
280
281	PTR_ADD	t3, s1			# t3 <-- location to fix up in RAM
282	PTR_S	t8, 0(t3)
283
2842:
285	blt	t1, t2, 1b
286	 PTR_ADDIU t1, 2 * PTRSIZE	# each rel.dyn entry is 2*PTRSIZE bytes
287
288	/*
289	 * Flush caches to ensure our newly modified instructions are visible
290	 * to the instruction cache. We're still running with the old GOT, so
291	 * apply the reloc offset to the start address.
292	 */
293	PTR_LA	a0, __text_start
294	PTR_LA	a1, __text_end
295	PTR_SUB	a1, a1, a0
296	PTR_LA	t9, flush_cache
297	jalr	t9
298	 PTR_ADD	a0, s1
299
300	PTR_ADD	gp, s1			# adjust gp
301
302	/*
303	 * Clear BSS
304	 *
305	 * GOT is now relocated. Thus __bss_start and __bss_end can be
306	 * accessed directly via $gp.
307	 */
308	PTR_LA	t1, __bss_start		# t1 <-- __bss_start
309	PTR_LA	t2, __bss_end		# t2 <-- __bss_end
310
3111:
312	PTR_S	zero, 0(t1)
313	blt	t1, t2, 1b
314	 PTR_ADDIU t1, PTRSIZE
315
316	move	a0, s0			# a0 <-- gd
317	move	a1, s2
318	PTR_LA	t9, board_init_r
319	jr	t9
320	 move	ra, zero
321
322	END(relocate_code)
323