env: Convert CONFIG_ENV_IS_IN... to a choice

At present we support multiple environment drivers but there is not way to
select between them at run time. Also settings related to the position and
siz

env: Convert CONFIG_ENV_IS_IN... to a choice

At present we support multiple environment drivers but there is not way to
select between them at run time. Also settings related to the position and
size of the environment area are global (i.e. apply to all locations).

Until these limitations are removed we cannot really support more than one
environment location. Adjust the location to be a choice so that only one
can be selected. By default the environment is 'nowhere', meaning that the
environment exists only in memory and cannot be saved.

Also expand the help for the 'nowhere' option and move it to the top since
it is the default.

Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Move all of the imply logic to default X if Y so it works again]
Signed-off-by: Tom Rini <trini@konsulko.com>

show more ...

Convert CONFIG_ENV_IS_IN_FLASH to Kconfig

This converts the following to Kconfig:
CONFIG_ENV_IS_IN_FLASH

Signed-off-by: Simon Glass <sjg@chromium.org>

Convert CONFIG_ENV_IS_IN_MMC/NAND/UBI and NOWHERE to Kconfig

This converts the following to Kconfig:
CONFIG_ENV_IS_IN_MMC
CONFIG_ENV_IS_IN_NAND
CONFIG_ENV_IS_IN_UBI
CONFIG_ENV_IS_NOWHERE

Convert CONFIG_ENV_IS_IN_MMC/NAND/UBI and NOWHERE to Kconfig

This converts the following to Kconfig:
CONFIG_ENV_IS_IN_MMC
CONFIG_ENV_IS_IN_NAND
CONFIG_ENV_IS_IN_UBI
CONFIG_ENV_IS_NOWHERE

In fact this already exists for sunxi as a 'choice' config. However not
all the choices are available in Kconfig yet so we cannot use that. It
would lead to more than one option being set.

In addition, one purpose of this series is to allow the environment to be
stored in more than one place. So the existing choice is converted to a
normal config allowing each option to be set independently.

There are not many opportunities for Kconfig updates to reduce the size of
this patch. This was tested with

./tools/moveconfig.py -i CONFIG_ENV_IS_IN_MMC

And then manual updates. This is because for CHAIN_OF_TRUST boards they
can only have ENV_IS_NOWHERE set, so we enforce that via Kconfig logic
now.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>

show more ...

Merge branch 'master' of git://git.denx.de/u-boot-mips

boston: Setup memory ranges in FDT provided to Linux

The boston memory map isn't suited to the simple "all memory starting
from 0" approach that the MIPS arch_fixup_fdt() implementation takes.
Inste

boston: Setup memory ranges in FDT provided to Linux

The boston memory map isn't suited to the simple "all memory starting
from 0" approach that the MIPS arch_fixup_fdt() implementation takes.
Instead we need to indicate the first 256MiB of DDR from 0 and the rest
from 0x90000000. Implement ft_board_setup to do that.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

show more ...

boston: Move CM GCRs away from flash

Move the MIPS Coherence Manager (CM) Global Configuration Registers
(GCRs) away from the region of the physical address space which the
Boston board's parallel f

boston: Move CM GCRs away from flash

Move the MIPS Coherence Manager (CM) Global Configuration Registers
(GCRs) away from the region of the physical address space which the
Boston board's parallel flash is found in, such that we can access all
of flash without clobbering GCRs.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

show more ...

MIPS: Make CM GCR base configurable

Without adding a prompt for CONFIG_MIPS_CM_BASE, Kconfig doesn't allow
defconfigs to set it. Provide the prompt in order to allow for that.

Signed-off-by: Paul B

MIPS: Make CM GCR base configurable

Without adding a prompt for CONFIG_MIPS_CM_BASE, Kconfig doesn't allow
defconfigs to set it. Provide the prompt in order to allow for that.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

show more ...

Merge branch 'master' of git://git.denx.de/u-boot-mips

MIPS: add initial infrastructure for Broadcom MIPS SoCs

CFE checks CPU Thread in a different way (using register $22):
mfc0 t1, C0_BCM_CONFIG, 3 # $22
li t2, CP0_CMT_TPID # (1 << 31)
and t1, t2
bnez

MIPS: add initial infrastructure for Broadcom MIPS SoCs

CFE checks CPU Thread in a different way (using register $22):
mfc0 t1, C0_BCM_CONFIG, 3 # $22
li t2, CP0_CMT_TPID # (1 << 31)
and t1, t2
bnez t1, 2f # if we are running on thread 1, skip init
nop

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

show more ...

Merge branch 'master' of git://git.denx.de/u-boot-mips

MIPS: add possibility to setup initial stack and global data in SRAM

This adds a new Kconfig option CONFIG_MIPS_INIT_STACK_IN_SRAM which
a SoC can select if it supports some kind of SRAM. Together w

MIPS: add possibility to setup initial stack and global data in SRAM

This adds a new Kconfig option CONFIG_MIPS_INIT_STACK_IN_SRAM which
a SoC can select if it supports some kind of SRAM. Together with
CONFIG_SYS_INIT_SP_ADDR the initial stack and global data can be
set up in that SRAM. This can be used to provide a C environment
also for lowlevel_init().

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>

show more ...

MIPS: make inclusion of ROM exception vectors configurable

This adds a compile time option to include code for static
exception vectors. Static exception vectors are only needed,
when the U-Boot ent

MIPS: make inclusion of ROM exception vectors configurable

This adds a compile time option to include code for static
exception vectors. Static exception vectors are only needed,
when the U-Boot entry point is equal to the CPU reset exception
vector address. For instance this is the case when U-Boot is
used as ROM in Qemu or booted from parallel NOR flash. When
U-Boot is booted from RAM (e.g. loaded there by SPL), the
exception vectors need to be setup dynamically, which is done
in follow-up commits.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>

show more ...

Merge branch 'master' of git://git.denx.de/u-boot-mips

boston: Introduce support for the MIPS Boston development board

This patch introduces support for building U-Boot to run on the MIPS
Boston development board. This is a board built around an FPGA &

boston: Introduce support for the MIPS Boston development board

This patch introduces support for building U-Boot to run on the MIPS
Boston development board. This is a board built around an FPGA & an
Intel EG20T Platform Controller Hub, used largely as part of the
development of new CPUs and their software support. It is essentially
the successor to the older MIPS Malta board.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>

show more ...

MIPS: Malta: Enable CM & L2 support

Enable support for the MIPS Coherence Manager & L2 caches on the MIPS
Malta board, removing the need for us to attempt to bypass the L2 during
boot (which would f

MIPS: Malta: Enable CM & L2 support

Enable support for the MIPS Coherence Manager & L2 caches on the MIPS
Malta board, removing the need for us to attempt to bypass the L2 during
boot (which would fail with recent CPUs that expose L2 config via the CM
anyway).

Signed-off-by: Paul Burton <paul.burton@imgtec.com>

show more ...

MIPS: L2 cache support

This patch adds support for initialising & maintaining L2 caches on MIPS
systems. The L2 cache configuration may be advertised through either
coprocessor 0 or the MIPS Coheren

MIPS: L2 cache support

This patch adds support for initialising & maintaining L2 caches on MIPS
systems. The L2 cache configuration may be advertised through either
coprocessor 0 or the MIPS Coherence Manager depending upon the system,
and support for both is included.

If the L2 can be bypassed then we bypass it early in boot & initialise
the L1 caches first, such that we can start making use of the L1
instruction cache as early as possible. Otherwise we initialise the L2
first such that the L1s have no opportunity to generate access to the
uninitialised L2.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>

show more ...

MIPS: Map CM Global Control Registers

Map the Global Control Registers (GCRs) provided by the MIPS Coherence
Manager (CM) in preparation for using some of them in later patches.

Signed-off-by: Paul

MIPS: Map CM Global Control Registers

Map the Global Control Registers (GCRs) provided by the MIPS Coherence
Manager (CM) in preparation for using some of them in later patches.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>

show more ...

mips: Add MIPSfpga platform support

MIPSfpga is an FPGA based dev platform.

In a nutshell, its a microAptiv cpu core with lots of Xilinx IP blocks

The FPGA dev board used is the Nexys4DDR board by

mips: Add MIPSfpga platform support

MIPSfpga is an FPGA based dev platform.

In a nutshell, its a microAptiv cpu core with lots of Xilinx IP blocks

The FPGA dev board used is the Nexys4DDR board by Digilent.

For more information, check the Readme file in board/imgtec/xilfpga

Signed-off-by: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
Reviewed-by: Paul Burton <paul.burton@imgtec.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>

show more ...

Merge branch 'master' of git://git.denx.de/u-boot

Signed-off-by: Stefano Babic <sbabic@denx.de>

Merge branch 'master' of git://git.denx.de/u-boot-mips

MIPS: Make CONFIG_SYS_DCACHE_LINE_SIZE int, not hex

For consistency with the other cache-related Kconfig entries & the
values actually set by boards, make CONFIG_SYS_DCACHE_LINE_SIZE an int
entry in

MIPS: Make CONFIG_SYS_DCACHE_LINE_SIZE int, not hex

For consistency with the other cache-related Kconfig entries & the
values actually set by boards, make CONFIG_SYS_DCACHE_LINE_SIZE an int
entry instead of a hex entry.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Fixes: 372286217f05 ("MIPS: Split I & D cache line size config")

show more ...

Merge branch 'master' of git://git.denx.de/u-boot-mips

MIPS: Split I & D cache line size config

Allow L1 Icache & L1 Dcache line size to be specified separately, since
there's no architectural mandate that they be the same. The
[id]cache_line_size funct

MIPS: Split I & D cache line size config

Allow L1 Icache & L1 Dcache line size to be specified separately, since
there's no architectural mandate that they be the same. The
[id]cache_line_size functions are tidied up to take advantage of the
fact that the Kconfig entries are always present to simply check them
for zero rather than needing to #ifdef on their presence.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
[removed CONFIG_SYS_CACHELINE_SIZE in include/configs/pic32mzdask.h]
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>

show more ...

MIPS: Move cache sizes to Kconfig

Move details of the L1 cache line sizes & total sizes into Kconfig,
defaulting to 0. A new CONFIG_SYS_CACHE_SIZE_AUTO Kconfig entry is
introduced to allow platforms

MIPS: Move cache sizes to Kconfig

Move details of the L1 cache line sizes & total sizes into Kconfig,
defaulting to 0. A new CONFIG_SYS_CACHE_SIZE_AUTO Kconfig entry is
introduced to allow platforms to select auto-detection of cache sizes,
and it defaults to being enabled if none of the cache sizes are set by
the configuration (ie. sizes are all the default 0), and code is
adjusted to #ifdef on that rather than on the definition of the sizes
(which will always be defined even if 0).

Signed-off-by: Paul Burton <paul.burton@imgtec.com>

show more ...

MIPS: add tune for MIPS 34kc

Add tune Kconfig option for MIPS 34kc.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>