1menu "MIPS architecture" 2 depends on MIPS 3 4config SYS_ARCH 5 default "mips" 6 7config SYS_CPU 8 default "mips32" if CPU_MIPS32 9 default "mips64" if CPU_MIPS64 10 11choice 12 prompt "Target select" 13 optional 14 15config TARGET_QEMU_MIPS 16 bool "Support qemu-mips" 17 select SUPPORTS_BIG_ENDIAN 18 select SUPPORTS_LITTLE_ENDIAN 19 select SUPPORTS_CPU_MIPS32_R1 20 select SUPPORTS_CPU_MIPS32_R2 21 select SUPPORTS_CPU_MIPS64_R1 22 select SUPPORTS_CPU_MIPS64_R2 23 select ROM_EXCEPTION_VECTORS 24 25config TARGET_MALTA 26 bool "Support malta" 27 select DM 28 select DM_SERIAL 29 select DYNAMIC_IO_PORT_BASE 30 select MIPS_CM 31 select MIPS_L2_CACHE 32 select OF_CONTROL 33 select OF_ISA_BUS 34 select SUPPORTS_BIG_ENDIAN 35 select SUPPORTS_LITTLE_ENDIAN 36 select SUPPORTS_CPU_MIPS32_R1 37 select SUPPORTS_CPU_MIPS32_R2 38 select SUPPORTS_CPU_MIPS32_R6 39 select SUPPORTS_CPU_MIPS64_R1 40 select SUPPORTS_CPU_MIPS64_R2 41 select SUPPORTS_CPU_MIPS64_R6 42 select SWAP_IO_SPACE 43 select MIPS_L1_CACHE_SHIFT_6 44 select ROM_EXCEPTION_VECTORS 45 46config TARGET_VCT 47 bool "Support vct" 48 select SUPPORTS_BIG_ENDIAN 49 select SUPPORTS_CPU_MIPS32_R1 50 select SUPPORTS_CPU_MIPS32_R2 51 select SYS_MIPS_CACHE_INIT_RAM_LOAD 52 select ROM_EXCEPTION_VECTORS 53 54config TARGET_DBAU1X00 55 bool "Support dbau1x00" 56 select SUPPORTS_BIG_ENDIAN 57 select SUPPORTS_LITTLE_ENDIAN 58 select SUPPORTS_CPU_MIPS32_R1 59 select SUPPORTS_CPU_MIPS32_R2 60 select SYS_MIPS_CACHE_INIT_RAM_LOAD 61 select ROM_EXCEPTION_VECTORS 62 select MIPS_TUNE_4KC 63 64config TARGET_PB1X00 65 bool "Support pb1x00" 66 select SUPPORTS_LITTLE_ENDIAN 67 select SUPPORTS_CPU_MIPS32_R1 68 select SUPPORTS_CPU_MIPS32_R2 69 select SYS_MIPS_CACHE_INIT_RAM_LOAD 70 select ROM_EXCEPTION_VECTORS 71 select MIPS_TUNE_4KC 72 73config ARCH_ATH79 74 bool "Support QCA/Atheros ath79" 75 select OF_CONTROL 76 select DM 77 78config ARCH_BMIPS 79 bool "Support BMIPS SoCs" 80 select OF_CONTROL 81 select DM 82 select CLK 83 select CPU 84 select RAM 85 select SYSRESET 86 87config MACH_PIC32 88 bool "Support Microchip PIC32" 89 select OF_CONTROL 90 select DM 91 92config TARGET_BOSTON 93 bool "Support Boston" 94 select DM 95 select DM_SERIAL 96 select OF_CONTROL 97 select MIPS_CM 98 select MIPS_L1_CACHE_SHIFT_6 99 select MIPS_L2_CACHE 100 select SUPPORTS_BIG_ENDIAN 101 select SUPPORTS_LITTLE_ENDIAN 102 select SUPPORTS_CPU_MIPS32_R1 103 select SUPPORTS_CPU_MIPS32_R2 104 select SUPPORTS_CPU_MIPS32_R6 105 select SUPPORTS_CPU_MIPS64_R1 106 select SUPPORTS_CPU_MIPS64_R2 107 select SUPPORTS_CPU_MIPS64_R6 108 select ROM_EXCEPTION_VECTORS 109 110config TARGET_XILFPGA 111 bool "Support Imagination Xilfpga" 112 select OF_CONTROL 113 select DM 114 select DM_SERIAL 115 select DM_GPIO 116 select DM_ETH 117 select SUPPORTS_LITTLE_ENDIAN 118 select SUPPORTS_CPU_MIPS32_R1 119 select SUPPORTS_CPU_MIPS32_R2 120 select MIPS_L1_CACHE_SHIFT_4 121 select ROM_EXCEPTION_VECTORS 122 help 123 This supports IMGTEC MIPSfpga platform 124 125endchoice 126 127source "board/dbau1x00/Kconfig" 128source "board/imgtec/boston/Kconfig" 129source "board/imgtec/malta/Kconfig" 130source "board/imgtec/xilfpga/Kconfig" 131source "board/micronas/vct/Kconfig" 132source "board/pb1x00/Kconfig" 133source "board/qemu-mips/Kconfig" 134source "arch/mips/mach-ath79/Kconfig" 135source "arch/mips/mach-bmips/Kconfig" 136source "arch/mips/mach-pic32/Kconfig" 137 138if MIPS 139 140choice 141 prompt "Endianness selection" 142 help 143 Some MIPS boards can be configured for either little or big endian 144 byte order. These modes require different U-Boot images. In general there 145 is one preferred byteorder for a particular system but some systems are 146 just as commonly used in the one or the other endianness. 147 148config SYS_BIG_ENDIAN 149 bool "Big endian" 150 depends on SUPPORTS_BIG_ENDIAN 151 152config SYS_LITTLE_ENDIAN 153 bool "Little endian" 154 depends on SUPPORTS_LITTLE_ENDIAN 155 156endchoice 157 158choice 159 prompt "CPU selection" 160 default CPU_MIPS32_R2 161 162config CPU_MIPS32_R1 163 bool "MIPS32 Release 1" 164 depends on SUPPORTS_CPU_MIPS32_R1 165 select 32BIT 166 help 167 Choose this option to build an U-Boot for release 1 through 5 of the 168 MIPS32 architecture. 169 170config CPU_MIPS32_R2 171 bool "MIPS32 Release 2" 172 depends on SUPPORTS_CPU_MIPS32_R2 173 select 32BIT 174 help 175 Choose this option to build an U-Boot for release 2 through 5 of the 176 MIPS32 architecture. 177 178config CPU_MIPS32_R6 179 bool "MIPS32 Release 6" 180 depends on SUPPORTS_CPU_MIPS32_R6 181 select 32BIT 182 help 183 Choose this option to build an U-Boot for release 6 or later of the 184 MIPS32 architecture. 185 186config CPU_MIPS64_R1 187 bool "MIPS64 Release 1" 188 depends on SUPPORTS_CPU_MIPS64_R1 189 select 64BIT 190 help 191 Choose this option to build a kernel for release 1 through 5 of the 192 MIPS64 architecture. 193 194config CPU_MIPS64_R2 195 bool "MIPS64 Release 2" 196 depends on SUPPORTS_CPU_MIPS64_R2 197 select 64BIT 198 help 199 Choose this option to build a kernel for release 2 through 5 of the 200 MIPS64 architecture. 201 202config CPU_MIPS64_R6 203 bool "MIPS64 Release 6" 204 depends on SUPPORTS_CPU_MIPS64_R6 205 select 64BIT 206 help 207 Choose this option to build a kernel for release 6 or later of the 208 MIPS64 architecture. 209 210endchoice 211 212menu "General setup" 213 214config ROM_EXCEPTION_VECTORS 215 bool "Build U-Boot image with exception vectors" 216 help 217 Enable this to include exception vectors in the U-Boot image. This is 218 required if the U-Boot entry point is equal to the address of the 219 CPU reset exception vector (e.g. U-Boot as ROM loader in Qemu, 220 U-Boot booted from parallel NOR flash). 221 Disable this, if the U-Boot image is booted from DRAM (e.g. by SPL). 222 In that case the image size will be reduced by 0x500 bytes. 223 224config MIPS_CM_BASE 225 hex "MIPS CM GCR Base Address" 226 depends on MIPS_CM 227 default 0x16100000 if TARGET_BOSTON 228 default 0x1fbf8000 229 help 230 The physical base address at which to map the MIPS Coherence Manager 231 Global Configuration Registers (GCRs). This should be set such that 232 the GCRs occupy a region of the physical address space which is 233 otherwise unused, or at minimum that software doesn't need to access. 234 235endmenu 236 237menu "OS boot interface" 238 239config MIPS_BOOT_CMDLINE_LEGACY 240 bool "Hand over legacy command line to Linux kernel" 241 default y 242 help 243 Enable this option if you want U-Boot to hand over the Yamon-style 244 command line to the kernel. All bootargs will be prepared as argc/argv 245 compatible list. The argument count (argc) is stored in register $a0. 246 The address of the argument list (argv) is stored in register $a1. 247 248config MIPS_BOOT_ENV_LEGACY 249 bool "Hand over legacy environment to Linux kernel" 250 default y 251 help 252 Enable this option if you want U-Boot to hand over the Yamon-style 253 environment to the kernel. Information like memory size, initrd 254 address and size will be prepared as zero-terminated key/value list. 255 The address of the environment is stored in register $a2. 256 257config MIPS_BOOT_FDT 258 bool "Hand over a flattened device tree to Linux kernel" 259 default n 260 help 261 Enable this option if you want U-Boot to hand over a flattened 262 device tree to the kernel. According to UHI register $a0 will be set 263 to -2 and the FDT address is stored in $a1. 264 265endmenu 266 267config SUPPORTS_BIG_ENDIAN 268 bool 269 270config SUPPORTS_LITTLE_ENDIAN 271 bool 272 273config SUPPORTS_CPU_MIPS32_R1 274 bool 275 276config SUPPORTS_CPU_MIPS32_R2 277 bool 278 279config SUPPORTS_CPU_MIPS32_R6 280 bool 281 282config SUPPORTS_CPU_MIPS64_R1 283 bool 284 285config SUPPORTS_CPU_MIPS64_R2 286 bool 287 288config SUPPORTS_CPU_MIPS64_R6 289 bool 290 291config CPU_MIPS32 292 bool 293 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6 294 295config CPU_MIPS64 296 bool 297 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6 298 299config MIPS_TUNE_4KC 300 bool 301 302config MIPS_TUNE_14KC 303 bool 304 305config MIPS_TUNE_24KC 306 bool 307 308config MIPS_TUNE_34KC 309 bool 310 311config MIPS_TUNE_74KC 312 bool 313 314config 32BIT 315 bool 316 317config 64BIT 318 bool 319 320config SWAP_IO_SPACE 321 bool 322 323config SYS_MIPS_CACHE_INIT_RAM_LOAD 324 bool 325 326config MIPS_INIT_STACK_IN_SRAM 327 bool 328 default n 329 help 330 Select this if the initial stack frame could be setup in SRAM. 331 Normally the initial stack frame is set up in DRAM which is often 332 only available after lowlevel_init. With this option the initial 333 stack frame and the early C environment is set up before 334 lowlevel_init. Thus lowlevel_init does not need to be implemented 335 in assembler. 336 337config SYS_DCACHE_SIZE 338 int 339 default 0 340 help 341 The total size of the L1 Dcache, if known at compile time. 342 343config SYS_DCACHE_LINE_SIZE 344 int 345 default 0 346 help 347 The size of L1 Dcache lines, if known at compile time. 348 349config SYS_ICACHE_SIZE 350 int 351 default 0 352 help 353 The total size of the L1 ICache, if known at compile time. 354 355config SYS_ICACHE_LINE_SIZE 356 int 357 default 0 358 help 359 The size of L1 Icache lines, if known at compile time. 360 361config SYS_CACHE_SIZE_AUTO 362 def_bool y if SYS_DCACHE_SIZE = 0 && SYS_ICACHE_SIZE = 0 && \ 363 SYS_DCACHE_LINE_SIZE = 0 && SYS_ICACHE_LINE_SIZE = 0 364 help 365 Select this (or let it be auto-selected by not defining any cache 366 sizes) in order to allow U-Boot to automatically detect the sizes 367 of caches at runtime. This has a small cost in code size & runtime 368 so if you know the cache configuration for your system at compile 369 time it would be beneficial to configure it. 370 371config MIPS_L1_CACHE_SHIFT_4 372 bool 373 374config MIPS_L1_CACHE_SHIFT_5 375 bool 376 377config MIPS_L1_CACHE_SHIFT_6 378 bool 379 380config MIPS_L1_CACHE_SHIFT_7 381 bool 382 383config MIPS_L1_CACHE_SHIFT 384 int 385 default "7" if MIPS_L1_CACHE_SHIFT_7 386 default "6" if MIPS_L1_CACHE_SHIFT_6 387 default "5" if MIPS_L1_CACHE_SHIFT_5 388 default "4" if MIPS_L1_CACHE_SHIFT_4 389 default "5" 390 391config MIPS_L2_CACHE 392 bool 393 help 394 Select this if your system includes an L2 cache and you want U-Boot 395 to initialise & maintain it. 396 397config DYNAMIC_IO_PORT_BASE 398 bool 399 400config MIPS_CM 401 bool 402 help 403 Select this if your system contains a MIPS Coherence Manager and you 404 wish U-Boot to configure it or make use of it to retrieve system 405 information such as cache configuration. 406 407endif 408 409endmenu 410