1menu "MIPS architecture" 2 depends on MIPS 3 4config SYS_ARCH 5 default "mips" 6 7config SYS_CPU 8 default "mips32" if CPU_MIPS32 9 default "mips64" if CPU_MIPS64 10 11choice 12 prompt "Target select" 13 optional 14 15config TARGET_QEMU_MIPS 16 bool "Support qemu-mips" 17 select SUPPORTS_BIG_ENDIAN 18 select SUPPORTS_LITTLE_ENDIAN 19 select SUPPORTS_CPU_MIPS32_R1 20 select SUPPORTS_CPU_MIPS32_R2 21 select SUPPORTS_CPU_MIPS64_R1 22 select SUPPORTS_CPU_MIPS64_R2 23 24config TARGET_MALTA 25 bool "Support malta" 26 select DM 27 select DM_SERIAL 28 select DYNAMIC_IO_PORT_BASE 29 select OF_CONTROL 30 select OF_ISA_BUS 31 select SUPPORTS_BIG_ENDIAN 32 select SUPPORTS_LITTLE_ENDIAN 33 select SUPPORTS_CPU_MIPS32_R1 34 select SUPPORTS_CPU_MIPS32_R2 35 select SUPPORTS_CPU_MIPS32_R6 36 select SUPPORTS_CPU_MIPS64_R1 37 select SUPPORTS_CPU_MIPS64_R2 38 select SUPPORTS_CPU_MIPS64_R6 39 select SWAP_IO_SPACE 40 select MIPS_L1_CACHE_SHIFT_6 41 42config TARGET_VCT 43 bool "Support vct" 44 select SUPPORTS_BIG_ENDIAN 45 select SUPPORTS_CPU_MIPS32_R1 46 select SUPPORTS_CPU_MIPS32_R2 47 select SYS_MIPS_CACHE_INIT_RAM_LOAD 48 49config TARGET_DBAU1X00 50 bool "Support dbau1x00" 51 select SUPPORTS_BIG_ENDIAN 52 select SUPPORTS_LITTLE_ENDIAN 53 select SUPPORTS_CPU_MIPS32_R1 54 select SUPPORTS_CPU_MIPS32_R2 55 select SYS_MIPS_CACHE_INIT_RAM_LOAD 56 select MIPS_TUNE_4KC 57 58config TARGET_PB1X00 59 bool "Support pb1x00" 60 select SUPPORTS_LITTLE_ENDIAN 61 select SUPPORTS_CPU_MIPS32_R1 62 select SUPPORTS_CPU_MIPS32_R2 63 select SYS_MIPS_CACHE_INIT_RAM_LOAD 64 select MIPS_TUNE_4KC 65 66config ARCH_ATH79 67 bool "Support QCA/Atheros ath79" 68 select OF_CONTROL 69 select DM 70 71config MACH_PIC32 72 bool "Support Microchip PIC32" 73 select OF_CONTROL 74 select DM 75 76config TARGET_XILFPGA 77 bool "Support Imagination Xilfpga" 78 select OF_CONTROL 79 select DM 80 select DM_SERIAL 81 select DM_GPIO 82 select DM_ETH 83 select SUPPORTS_LITTLE_ENDIAN 84 select SUPPORTS_CPU_MIPS32_R1 85 select SUPPORTS_CPU_MIPS32_R2 86 select MIPS_L1_CACHE_SHIFT_4 87 help 88 This supports IMGTEC MIPSfpga platform 89 90endchoice 91 92source "board/dbau1x00/Kconfig" 93source "board/imgtec/malta/Kconfig" 94source "board/imgtec/xilfpga/Kconfig" 95source "board/micronas/vct/Kconfig" 96source "board/pb1x00/Kconfig" 97source "board/qemu-mips/Kconfig" 98source "arch/mips/mach-ath79/Kconfig" 99source "arch/mips/mach-pic32/Kconfig" 100 101if MIPS 102 103choice 104 prompt "Endianness selection" 105 help 106 Some MIPS boards can be configured for either little or big endian 107 byte order. These modes require different U-Boot images. In general there 108 is one preferred byteorder for a particular system but some systems are 109 just as commonly used in the one or the other endianness. 110 111config SYS_BIG_ENDIAN 112 bool "Big endian" 113 depends on SUPPORTS_BIG_ENDIAN 114 115config SYS_LITTLE_ENDIAN 116 bool "Little endian" 117 depends on SUPPORTS_LITTLE_ENDIAN 118 119endchoice 120 121choice 122 prompt "CPU selection" 123 default CPU_MIPS32_R2 124 125config CPU_MIPS32_R1 126 bool "MIPS32 Release 1" 127 depends on SUPPORTS_CPU_MIPS32_R1 128 select 32BIT 129 help 130 Choose this option to build an U-Boot for release 1 through 5 of the 131 MIPS32 architecture. 132 133config CPU_MIPS32_R2 134 bool "MIPS32 Release 2" 135 depends on SUPPORTS_CPU_MIPS32_R2 136 select 32BIT 137 help 138 Choose this option to build an U-Boot for release 2 through 5 of the 139 MIPS32 architecture. 140 141config CPU_MIPS32_R6 142 bool "MIPS32 Release 6" 143 depends on SUPPORTS_CPU_MIPS32_R6 144 select 32BIT 145 help 146 Choose this option to build an U-Boot for release 6 or later of the 147 MIPS32 architecture. 148 149config CPU_MIPS64_R1 150 bool "MIPS64 Release 1" 151 depends on SUPPORTS_CPU_MIPS64_R1 152 select 64BIT 153 help 154 Choose this option to build a kernel for release 1 through 5 of the 155 MIPS64 architecture. 156 157config CPU_MIPS64_R2 158 bool "MIPS64 Release 2" 159 depends on SUPPORTS_CPU_MIPS64_R2 160 select 64BIT 161 help 162 Choose this option to build a kernel for release 2 through 5 of the 163 MIPS64 architecture. 164 165config CPU_MIPS64_R6 166 bool "MIPS64 Release 6" 167 depends on SUPPORTS_CPU_MIPS64_R6 168 select 64BIT 169 help 170 Choose this option to build a kernel for release 6 or later of the 171 MIPS64 architecture. 172 173endchoice 174 175menu "OS boot interface" 176 177config MIPS_BOOT_CMDLINE_LEGACY 178 bool "Hand over legacy command line to Linux kernel" 179 default y 180 help 181 Enable this option if you want U-Boot to hand over the Yamon-style 182 command line to the kernel. All bootargs will be prepared as argc/argv 183 compatible list. The argument count (argc) is stored in register $a0. 184 The address of the argument list (argv) is stored in register $a1. 185 186config MIPS_BOOT_ENV_LEGACY 187 bool "Hand over legacy environment to Linux kernel" 188 default y 189 help 190 Enable this option if you want U-Boot to hand over the Yamon-style 191 environment to the kernel. Information like memory size, initrd 192 address and size will be prepared as zero-terminated key/value list. 193 The address of the environment is stored in register $a2. 194 195config MIPS_BOOT_FDT 196 bool "Hand over a flattened device tree to Linux kernel" 197 default n 198 help 199 Enable this option if you want U-Boot to hand over a flattened 200 device tree to the kernel. According to UHI register $a0 will be set 201 to -2 and the FDT address is stored in $a1. 202 203endmenu 204 205config SUPPORTS_BIG_ENDIAN 206 bool 207 208config SUPPORTS_LITTLE_ENDIAN 209 bool 210 211config SUPPORTS_CPU_MIPS32_R1 212 bool 213 214config SUPPORTS_CPU_MIPS32_R2 215 bool 216 217config SUPPORTS_CPU_MIPS32_R6 218 bool 219 220config SUPPORTS_CPU_MIPS64_R1 221 bool 222 223config SUPPORTS_CPU_MIPS64_R2 224 bool 225 226config SUPPORTS_CPU_MIPS64_R6 227 bool 228 229config CPU_MIPS32 230 bool 231 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6 232 233config CPU_MIPS64 234 bool 235 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6 236 237config MIPS_TUNE_4KC 238 bool 239 240config MIPS_TUNE_14KC 241 bool 242 243config MIPS_TUNE_24KC 244 bool 245 246config MIPS_TUNE_34KC 247 bool 248 249config MIPS_TUNE_74KC 250 bool 251 252config 32BIT 253 bool 254 255config 64BIT 256 bool 257 258config SWAP_IO_SPACE 259 bool 260 261config SYS_MIPS_CACHE_INIT_RAM_LOAD 262 bool 263 264config SYS_DCACHE_SIZE 265 int 266 default 0 267 help 268 The total size of the L1 Dcache, if known at compile time. 269 270config SYS_DCACHE_LINE_SIZE 271 int 272 default 0 273 help 274 The size of L1 Dcache lines, if known at compile time. 275 276config SYS_ICACHE_SIZE 277 int 278 default 0 279 help 280 The total size of the L1 ICache, if known at compile time. 281 282config SYS_ICACHE_LINE_SIZE 283 int 284 default 0 285 help 286 The size of L1 Icache lines, if known at compile time. 287 288config SYS_CACHE_SIZE_AUTO 289 def_bool y if SYS_DCACHE_SIZE = 0 && SYS_ICACHE_SIZE = 0 && \ 290 SYS_DCACHE_LINE_SIZE = 0 && SYS_ICACHE_LINE_SIZE = 0 291 help 292 Select this (or let it be auto-selected by not defining any cache 293 sizes) in order to allow U-Boot to automatically detect the sizes 294 of caches at runtime. This has a small cost in code size & runtime 295 so if you know the cache configuration for your system at compile 296 time it would be beneficial to configure it. 297 298config MIPS_L1_CACHE_SHIFT_4 299 bool 300 301config MIPS_L1_CACHE_SHIFT_5 302 bool 303 304config MIPS_L1_CACHE_SHIFT_6 305 bool 306 307config MIPS_L1_CACHE_SHIFT_7 308 bool 309 310config MIPS_L1_CACHE_SHIFT 311 int 312 default "7" if MIPS_L1_CACHE_SHIFT_7 313 default "6" if MIPS_L1_CACHE_SHIFT_6 314 default "5" if MIPS_L1_CACHE_SHIFT_5 315 default "4" if MIPS_L1_CACHE_SHIFT_4 316 default "5" 317 318config DYNAMIC_IO_PORT_BASE 319 bool 320 321endif 322 323endmenu 324