arm: add spl relocation support for armv8

Relocate spl itself to a high memory.

Change-Id: Ia69f05449a0a8e4f07cc6d37a2486c3cd2aa7176
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>

arm: armv7/8: add CONFIG_ARM_CPU_SUSPEND definition

Make it as a optional choice.

Change-Id: I87c5d8ce863eb64f3922fb4124e1f4a6aaf79257
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>

armv7: sleep.S: support other v7 cpu

Change-Id: Ib1b1cb973054c9faa6a11da8fc1ad7f1d5aec214
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>

armv7: sleep.S: rename _suspend_gd to __suspend_gd

Change-Id: I97911822c5616dbcbb3b28a156a3759f3b6b2af3
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>

armv7: add -funwind-tables compile option to support stacktrace

Change-Id: Icfa223397e05dcd42ea3c12275385104bf275213
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>

arm: lib: add arm32/64 stacktrace support

This patch supports dump arm32/64 stacktrace as the format of raw
address info. The U-Boot symbol table is not available now, please
use ./scripts/stacktrac

arm: lib: add arm32/64 stacktrace support

This patch supports dump arm32/64 stacktrace as the format of raw
address info. The U-Boot symbol table is not available now, please
use ./scripts/stacktrace.sh script to parse stacktrace info with command:

./scripts/stacktrace.sh <file> // stacktrace info file

Example on RK3399:
Call trace:
PC: [< 00258a7c >] dwc3_gadget_uboot_handle_interrupt+0xa0/0x5bc
LR: [< 002052f8 >] usb_gadget_handle_interrupts+0x10/0x1c

Stack:
[< 00258a7c >] dwc3_gadget_uboot_handle_interrupt+0xa0/0x5bc
[< 0025bd6c >] sleep_thread.isra.20+0xb0/0x114
[< 0025cf58 >] fsg_main_thread+0x2c8/0x1814
[< 0020db58 >] do_rkusb+0x250/0x338
[< 00226a00 >] cmd_process+0xac/0xe0
[< 00212df4 >] run_list_real+0x6fc/0x72c
[< 00212f94 >] parse_stream_outer+0x170/0x67c
[< 002126e0 >] parse_string_outer+0xdc/0xf4
[< 00212bb0 >] run_list_real+0x4b8/0x72c
[< 00212f94 >] parse_stream_outer+0x170/0x67c
[< 00212698 >] parse_string_outer+0x94/0xf4
[< 00225f30 >] run_command_list+0x38/0x90
[< 00202d08 >] rockchip_dnl_mode_check+0x4c/0xd4
[< 00202db0 >] setup_boot_mode+0x20/0xf0
[< 00203010 >] board_late_init+0x10/0x40
[< 0027071c >] initcall_run_list+0x44/0x80
[< 00213d68 >] board_init_r+0x20/0x24

The "dump_stack()" is available to trigger stacktrace.

Change-Id: Ib1423269dd255fa4a34231489cd3b7e6ddd22540
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>

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UPSTREAM: libfdt: move headers to <linux/libfdt.h> and <linux/libfdt_env.h>

Thomas reported U-Boot failed to build host tools if libfdt-devel
package is installed because tools include libfdt header

UPSTREAM: libfdt: move headers to <linux/libfdt.h> and <linux/libfdt_env.h>

Thomas reported U-Boot failed to build host tools if libfdt-devel
package is installed because tools include libfdt headers from
/usr/include/ instead of using internal ones.

This commit moves the header code:
include/libfdt.h -> include/linux/libfdt.h
include/libfdt_env.h -> include/linux/libfdt_env.h

and replaces include directives:
#include <libfdt.h> -> #include <linux/libfdt.h>
#include <libfdt_env.h> -> #include <linux/libfdt_env.h>

Change-Id: I6c0f7e50e8b571106627f25ddac008a62bd2994e
Reported-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>

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rockchip: ARM: tpl: add TPL_TINY_FRAMEWORK flow for arm

If sram size is small for TPL build, it can defined
CONFIG_TPL_TINY_FRAMEWORK to reduce TPL size.
For ARM if defined CONFIG_TPL_TINY_FRAMEWORK

rockchip: ARM: tpl: add TPL_TINY_FRAMEWORK flow for arm

If sram size is small for TPL build, it can defined
CONFIG_TPL_TINY_FRAMEWORK to reduce TPL size.
For ARM if defined CONFIG_TPL_TINY_FRAMEWORK when build TPL, after
save_boot_params(), it jump to board_init_f() directly, then return to
maskrom. and stack also use maskrom defined result, never change the SP.

Change-Id: I9a90d031a5d200f86c437175e9ea47e8a34062ac
Signed-off-by: Zhihuan He <huan.he@rock-chips.com>

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rockchip: ARM64: tpl: modify TPL_TINY_FRAMEWORK flow to reduce code size

If sram size is small for TPL build, it can defined
CONFIG_TPL_TINY_FRAMEWORK to reduce TPL size.
For ARM64 if defined CONFIG

rockchip: ARM64: tpl: modify TPL_TINY_FRAMEWORK flow to reduce code size

If sram size is small for TPL build, it can defined
CONFIG_TPL_TINY_FRAMEWORK to reduce TPL size.
For ARM64 if defined CONFIG_TPL_TINY_FRAMEWORK when build TPL, after
save_boot_params(), it jump to board_init_f() directly, then return to
maskrom. and stack also use maskrom defined result, never change the SP.

Change-Id: I80dc414fcc276f5ea2c09afd6d1eb16e2f2f4cf6
Signed-off-by: YouMin Chen <cym@rock-chips.com>

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armv8: exceptions: optimize exception regs info

Add arm core registers bits description, it looks like:

Relocate offset = 000000003db55000
* ELR(PC) = 000000000025bd78
* LR = 0000000

armv8: exceptions: optimize exception regs info

Add arm core registers bits description, it looks like:

Relocate offset = 000000003db55000
* ELR(PC) = 000000000025bd78
* LR = 000000000025def4
* SP = 0000000039d4a6b0

* ESR_EL2 = 0000000040732550
EC[31:26] == 001100, Exception from an MCRR or MRRC access
IL[25] == 0, 16-bit instruction trapped

* DAIF = 00000000000003c0
D[9] == 1, DBG masked
A[8] == 1, ABORT masked
I[7] == 1, IRQ masked
F[6] == 1, FIQ masked

* SPSR_EL2 = 0000000080000349
D[9] == 1, DBG masked
A[8] == 1, ABORT masked
I[7] == 0, IRQ not masked
F[6] == 1, FIQ masked
M[4] == 0, Exception taken from AArch64
M[3:0] == 1001, EL2h

* SCTLR_EL2 = 0000000030c51835
I[12] == 1, Icaches enabled
C[2] == 1, Dcache enabled
M[0] == 1, MMU enabled

* VBAR_EL2 = 000000003dd55800
* HCR_EL2 = 000000000800003a
* TTBR0_EL2 = 000000003fff0000

x0 : 00000000ff300000 x1 : 0000000054808028
x2 : 000000000000002f x3 : 00000000ff160000
x4 : 0000000039d7fe80 x5 : 000000003de24ab0
......
x28: 0000000039d81ef0 x29: 0000000039d4a910

Change-Id: I828cafc961fdc3fcb2aa08916a7e36f690627313
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>

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debug: convert to use pr_debug for pte init and find dev

These two op have too much print, convert to pr_debug and not print
by default.

Change-Id: I5b3c738db783419717441e24ee0b04ab6f02d61e
Signed-

debug: convert to use pr_debug for pte init and find dev

These two op have too much print, convert to pr_debug and not print
by default.

Change-Id: I5b3c738db783419717441e24ee0b04ab6f02d61e
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>

show more ...

armv8: sleep.S: move data to data section

Change-Id: Ib70cd8afb937882de9a067f3424fc4b6a399a22e
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>

Move CONFIG_PANIC_HANG to Kconfig

Freescale (NXP) boards have lots of defconfig files per board.
I used "imply PANIC_HANG" for them.

Change-Id: I56347810ee33ccd8bb3553b0ee95b858e827ce9b
Signed-off-

Move CONFIG_PANIC_HANG to Kconfig

Freescale (NXP) boards have lots of defconfig files per board.
I used "imply PANIC_HANG" for them.

Change-Id: I56347810ee33ccd8bb3553b0ee95b858e827ce9b
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 7e3caa81e0e9cc5e2beed4a3a1c334e2119f4498)

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UPSTREAM: armv8: mmu: fix page table mapping

To page mapping the lowest 2 bits needs to be 0x3.
If not fix this, the final lowest 3 bits for page mapping is 0x1
which is marked as reserved.

Change-

UPSTREAM: armv8: mmu: fix page table mapping

To page mapping the lowest 2 bits needs to be 0x3.
If not fix this, the final lowest 3 bits for page mapping is 0x1
which is marked as reserved.

Change-Id: I5ac722421b46514736d93452aab68debe8aabfe5
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 90351547ceeb76c1337757c51af0fb5a2c30bd02)

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UPSTREAM: armv8: shrink exception table code

In the moment our exception entry code needs 34 instructions, so we
can't use put it directly into the table entry, which offers "only"
32 instructions t

UPSTREAM: armv8: shrink exception table code

In the moment our exception entry code needs 34 instructions, so we
can't use put it directly into the table entry, which offers "only"
32 instructions there. Right now we just put an unconditional branch
there, then use a macro to place the 34 instructions *per entry* after
that. That effectivly doubles the size of our exception table, which
is quite a waste, given that we use it mostly for debugging purposes.

Since the register saving part is actually identical, let's just convert
that macro into a function, and "bl" into it directly from the exception
slot, of course after having saved at least the original LR.
This saves us about 950 bytes of code, which is quite a relief for some
tight SPLs, in particular the 64-bit Allwinner ones.

Change-Id: I3d156413396f2a304773ef3a202f73d47cf65531
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 78ad457b2dbd0fe6cdc7ea42a69774a72ed007b9)

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UPSTREAM: tools: mkimage: Extend mkimage to also include pmufw

The patch is adding external pmufw "Platform Management Unit firmware"
to boot.bin image. Boot.bin is a Xilinx format which bootrom is

UPSTREAM: tools: mkimage: Extend mkimage to also include pmufw

The patch is adding external pmufw "Platform Management Unit firmware"
to boot.bin image. Boot.bin is a Xilinx format which bootrom is capable
to read and boot the system. pmufw is copied to the header data section
follows by u-boot-spl.bin. pmufw is consumed by PMU unit (Microblaze)
and SPL runs on a53-0.

This is generated command line when PMUFW_INIT_FILE is setup.

./tools/mkimage -T zynqmpimage -R ./"" -n
./"board/xilinx/zynqmp/pmufw.bin" -d spl/u-boot-spl.bin spl/boot.bin

Change-Id: I74fc17513dd99b876ab9c08ded6ad41a7b0cd3de
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit c85a6b79d10ed8a098997370cbc4fb233ddcb13b)

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UPSTREAM: arm64: support running at addr other than linked to

This is required in the case where U-Boot is typically loaded and run at
a particular address, but for some reason the RAM at that locat

UPSTREAM: arm64: support running at addr other than linked to

This is required in the case where U-Boot is typically loaded and run at
a particular address, but for some reason the RAM at that location is not
available, e.g. due to memory fragmentation loading other boot binaries or
firmware, splitting an SMP complex between various different OSs without
using e.g. the EL2 second-stage page tables to hide the memory asignments,
or due to known ECC failures.

Change-Id: I2fd535325517921c6036188b74ab4facd37b7118
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 49e93875a62fb9e96a4a7483b9bd5d8ae27ea76e)

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UPSTREAM: spl: fix assignment of board info to global data

Commit 15eb1d43bf47 ("spl: reorder the assignment of board info to
global data") intended to move assignment of board info earlier,
into bo

UPSTREAM: spl: fix assignment of board info to global data

Commit 15eb1d43bf47 ("spl: reorder the assignment of board info to
global data") intended to move assignment of board info earlier,
into board_init_r(). However, function preload_console_init() is
called either from spl_board_init() or from board_init_f(). For the
latter case, the board info assignment is much earlier than proposed
board_init_r(). Create a new function to fill gd->bd and call this
function when needed.

Change-Id: I3e8da19121f5b82f116b9d051b75acdd777c2475
Signed-off-by: York Sun <york.sun@nxp.com>
CC: Lokesh Vutla <lokeshvutla@ti.com>
CC: Ravi Babu <ravibabu@ti.com>
CC: Lukasz Majewski <lukma@denx.de>
CC: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit d1fc0a31b5f307c92b7a047d4f90d5ad2e54cdcc)

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UPSTREAM: blk: Remove various places that do flush cache after read

All these places seem to inherit the codes from the MMC driver where
a FIXME was put in the comment. However the correct operation

UPSTREAM: blk: Remove various places that do flush cache after read

All these places seem to inherit the codes from the MMC driver where
a FIXME was put in the comment. However the correct operation after
read should be cache invalidate, not flush.

The underlying drivers should be responsible for the cache operation.
Remove these codes completely.

Change-Id: I8f04c721432753b34e85b19616a0b42d83a633eb
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: York Sun <york.sun@nxp.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: York Sun <york.sun@nxp.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 723b43daec7ee2ddb600cfcb9b0253d4a71c3915)

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armv7: start.S: enable ACTLR.SMP bit

For cortex-A7 core, when ACTLR.SMP is 0 during the processor
power-up and power-down procedures, the caches are disabled
regardless of the SCTLR.C bit setting. I

armv7: start.S: enable ACTLR.SMP bit

For cortex-A7 core, when ACTLR.SMP is 0 during the processor
power-up and power-down procedures, the caches are disabled
regardless of the SCTLR.C bit setting. It's similar for other
cortex A series core.

Change-Id: I69512787015d651fe5bb5d6961f5ed01c2505058
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>

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arm: irq: do not enable irq in SPL/TPL

Change-Id: I6a9b8b883ede2e45e2c5760c633f04bd9ab4fe4e
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>

arm: armv8: introduce cpu suspend and resume support

Just like linux, it supports cpu save and restore context
during enter and exit low power mode. With this patch, cpu
is able to suspend with core

arm: armv8: introduce cpu suspend and resume support

Just like linux, it supports cpu save and restore context
during enter and exit low power mode. With this patch, cpu
is able to suspend with core power off.

Workflow for trap into ATF for system suspend:
cpu_suspend
-> cpu_do_suspend
-> arch specific fn: int (*fn)(unsigned long)
-> psci_system_suspend(deliver 'cpu_resume()' address to ATF)
-> ATF system suspend
<- ATF system resume
<- cpu_resume
<- cpu_do_resume
next instruction

Notice: If needed, you should remember to save and restore GIC by yourself.

Change-Id: I7a7c4989ba0845f5b6880c55a6ea6c47724c99df
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>

show more ...

arm: armv7: introduce cpu suspend and resume support

Just like linux, it supports cpu save and restore context
during enter and exit low power mode. With this patch, cpu
is able to suspend with core

arm: armv7: introduce cpu suspend and resume support

Just like linux, it supports cpu save and restore context
during enter and exit low power mode. With this patch, cpu
is able to suspend with core power off.

Workflow for trap into ATF for system suspend:
cpu_suspend
-> cpu_do_suspend
-> arch specific fn: int (*fn)(unsigned long)
-> psci_system_suspend(deliver 'cpu_resume()' address to ATF)
-> ATF system suspend
<- ATF system resume
<- cpu_resume
<- cpu_do_resume
next instruction

Notice: If needed, you should remember to save and restore GIC by yourself.

Change-Id: I5cb6fb6ac5b6a7f4ec4a975b0fc38250b000b28e
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>

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UPSTREAM: arm: mark save_boot_params_ret as a function

As no '.type' was set for save_boot_params_ret in start.S, binutils
did not track whether it was emitted as A32 or T32. By properly
marking sa

UPSTREAM: arm: mark save_boot_params_ret as a function

As no '.type' was set for save_boot_params_ret in start.S, binutils
did not track whether it was emitted as A32 or T32. By properly
marking save_boot_params_ret as a potential function entry, we can
make sure that the compiler will insert the appropriate instructions
for branching to save_boot_params_ret both for call-sites emitted as
A32 and T32.

Change-Id: I51807d61cd8655853f672ab0baeae641b16a0493
Reported-by: Andy Yan <andy.yan@rock-chips.com>
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Andy Yan <andy.yan@rock-chips.com>
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>

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ARM: add support for irq interrup framework

both GICV2 and GICV3 are supported

Change-Id: Ie928cc781c0e0830b98d12c4033e45a43befc2ff
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>