| 40aadf92 | 06-Aug-2013 |
Taras Kondratiuk <taras@ti.com> |
ARM: OMAP4470: Add voltage and dpll data
OMAP4470 reference design uses TWL6032 PMIC with a following connection scheme: VDD_CORE = TWL6032 SMPS2 VDD_MPU = TWL6032 SMPS1 VDD_IVA = TWL6032 SM
ARM: OMAP4470: Add voltage and dpll data
OMAP4470 reference design uses TWL6032 PMIC with a following connection scheme: VDD_CORE = TWL6032 SMPS2 VDD_MPU = TWL6032 SMPS1 VDD_IVA = TWL6032 SMPS5
Set voltage and frequency values according to OMAP4470 Data Manual Operating Condition Addendum v0.7
Signed-off-by: Taras Kondratiuk <taras@ti.com>
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| e08d6f3a | 26-Jun-2013 |
Bo Shen <voice.shen@atmel.com> |
arm: atmel: add gmac support for sama5d3xek board
add gmac support for sama5d3xek board, the gmac embedded in: - sama5d33, sama5d34, sama5d35
Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-
arm: atmel: add gmac support for sama5d3xek board
add gmac support for sama5d3xek board, the gmac embedded in: - sama5d33, sama5d34, sama5d35
Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
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| 9c8deaee | 05-Aug-2013 |
Heiko Schocher <hs@denx.de> |
arm, da850: enable the correct uart in arch_cpu_init()
in arch_cpu_init() uart2 is fix enabled, without reference the setting from CONFIG_SYS_NS16550_COM1. Use the setting from CONFIG_SYS_NS16550_CO
arm, da850: enable the correct uart in arch_cpu_init()
in arch_cpu_init() uart2 is fix enabled, without reference the setting from CONFIG_SYS_NS16550_COM1. Use the setting from CONFIG_SYS_NS16550_COM1 for enabling the console.
Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Cc: Tom Rini <tom.rini@gmail.com> Cc: Christian Riesch <christian.riesch@omicron.at>
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| 0474fb0e | 06-Aug-2013 |
Taras Kondratiuk <taras@ti.com> |
omap: emif: Set initial DDR PHY config first
Commit "OMAP5: emif/ddr: Change emif settings as required for ES1.0 silicon" (f40107345cbcd6e0d1747eda45e76c4e2a6df0db) changed sequence to set final DDR
omap: emif: Set initial DDR PHY config first
Commit "OMAP5: emif/ddr: Change emif settings as required for ES1.0 silicon" (f40107345cbcd6e0d1747eda45e76c4e2a6df0db) changed sequence to set final DDR PHY config register value at the beginning. Looks like it was made by mistake and should be reverted.
Signed-off-by: Taras Kondratiuk <taras@ti.com>
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| a704a6d6 | 09-Jul-2013 |
Naumann Andreas <ANaumann@ultratronik.de> |
ARM: omap3: Implement dpll5 (HSUSB clk) workaround for OMAP36xx/AM/DM37xx according to errata sprz318e.
In chapter 'Advisory 2.1 USB Host Clock Drift Causes USB Spec Non-compliance in Certain Config
ARM: omap3: Implement dpll5 (HSUSB clk) workaround for OMAP36xx/AM/DM37xx according to errata sprz318e.
In chapter 'Advisory 2.1 USB Host Clock Drift Causes USB Spec Non-compliance in Certain Configurations' of the TI Errata it is recommended to use certain div/mult values for the DPLL5 clock setup. So far u-boot used the old 34xx values, so I added the errata recommended values specificly for 36xx init only. Also, the FSEL registers exist no longer, so removed them from init.
Tested this on a AM3703 board with 19.2MHz oscillator, which previously couldnt lock the dpll5 (kernel complained). As a consequence the EHCI USB port wasnt usable in U-Boot and kernel. With this patch, kernel panics disappear and USB working fine in u-boot and kernel.
Signed-off-by: Andreas Naumann <anaumann@ultratronik.de> [trini: Add extern to <asm/arch-omap3/clock.h> Signed-off-by: Tom Rini <trini@ti.com>
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| 39523bef | 08-May-2013 |
Michal Simek <michal.simek@xilinx.com> |
zynq: slcr: Wait 100ms till clk is properly setup
If you don't wait you will loose the first sent packet even all bits in emacps are correctly setup.
Signed-off-by: Michal Simek <michal.simek@xilin
zynq: slcr: Wait 100ms till clk is properly setup
If you don't wait you will loose the first sent packet even all bits in emacps are correctly setup.
Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
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