1 /* 2 * board.c 3 * 4 * Board functions for TI AM335X based boards 5 * 6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #include <common.h> 12 #include <errno.h> 13 #include <spl.h> 14 #include <asm/arch/cpu.h> 15 #include <asm/arch/hardware.h> 16 #include <asm/arch/omap.h> 17 #include <asm/arch/ddr_defs.h> 18 #include <asm/arch/clock.h> 19 #include <asm/arch/gpio.h> 20 #include <asm/arch/mmc_host_def.h> 21 #include <asm/arch/sys_proto.h> 22 #include <asm/arch/mem.h> 23 #include <asm/io.h> 24 #include <asm/emif.h> 25 #include <asm/gpio.h> 26 #include <i2c.h> 27 #include <miiphy.h> 28 #include <cpsw.h> 29 #include "board.h" 30 31 DECLARE_GLOBAL_DATA_PTR; 32 33 static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; 34 35 /* MII mode defines */ 36 #define MII_MODE_ENABLE 0x0 37 #define RGMII_MODE_ENABLE 0x3A 38 39 /* GPIO that controls power to DDR on EVM-SK */ 40 #define GPIO_DDR_VTT_EN 7 41 42 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; 43 44 /* 45 * Read header information from EEPROM into global structure. 46 */ 47 static int read_eeprom(struct am335x_baseboard_id *header) 48 { 49 /* Check if baseboard eeprom is available */ 50 if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) { 51 puts("Could not probe the EEPROM; something fundamentally " 52 "wrong on the I2C bus.\n"); 53 return -ENODEV; 54 } 55 56 /* read the eeprom using i2c */ 57 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header, 58 sizeof(struct am335x_baseboard_id))) { 59 puts("Could not read the EEPROM; something fundamentally" 60 " wrong on the I2C bus.\n"); 61 return -EIO; 62 } 63 64 if (header->magic != 0xEE3355AA) { 65 /* 66 * read the eeprom using i2c again, 67 * but use only a 1 byte address 68 */ 69 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header, 70 sizeof(struct am335x_baseboard_id))) { 71 puts("Could not read the EEPROM; something " 72 "fundamentally wrong on the I2C bus.\n"); 73 return -EIO; 74 } 75 76 if (header->magic != 0xEE3355AA) { 77 printf("Incorrect magic number (0x%x) in EEPROM\n", 78 header->magic); 79 return -EINVAL; 80 } 81 } 82 83 return 0; 84 } 85 86 #if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT) 87 static const struct ddr_data ddr2_data = { 88 .datardsratio0 = ((MT47H128M16RT25E_RD_DQS<<30) | 89 (MT47H128M16RT25E_RD_DQS<<20) | 90 (MT47H128M16RT25E_RD_DQS<<10) | 91 (MT47H128M16RT25E_RD_DQS<<0)), 92 .datawdsratio0 = ((MT47H128M16RT25E_WR_DQS<<30) | 93 (MT47H128M16RT25E_WR_DQS<<20) | 94 (MT47H128M16RT25E_WR_DQS<<10) | 95 (MT47H128M16RT25E_WR_DQS<<0)), 96 .datawiratio0 = ((MT47H128M16RT25E_PHY_WRLVL<<30) | 97 (MT47H128M16RT25E_PHY_WRLVL<<20) | 98 (MT47H128M16RT25E_PHY_WRLVL<<10) | 99 (MT47H128M16RT25E_PHY_WRLVL<<0)), 100 .datagiratio0 = ((MT47H128M16RT25E_PHY_GATELVL<<30) | 101 (MT47H128M16RT25E_PHY_GATELVL<<20) | 102 (MT47H128M16RT25E_PHY_GATELVL<<10) | 103 (MT47H128M16RT25E_PHY_GATELVL<<0)), 104 .datafwsratio0 = ((MT47H128M16RT25E_PHY_FIFO_WE<<30) | 105 (MT47H128M16RT25E_PHY_FIFO_WE<<20) | 106 (MT47H128M16RT25E_PHY_FIFO_WE<<10) | 107 (MT47H128M16RT25E_PHY_FIFO_WE<<0)), 108 .datawrsratio0 = ((MT47H128M16RT25E_PHY_WR_DATA<<30) | 109 (MT47H128M16RT25E_PHY_WR_DATA<<20) | 110 (MT47H128M16RT25E_PHY_WR_DATA<<10) | 111 (MT47H128M16RT25E_PHY_WR_DATA<<0)), 112 .datauserank0delay = MT47H128M16RT25E_PHY_RANK0_DELAY, 113 .datadldiff0 = PHY_DLL_LOCK_DIFF, 114 }; 115 116 static const struct cmd_control ddr2_cmd_ctrl_data = { 117 .cmd0csratio = MT47H128M16RT25E_RATIO, 118 .cmd0dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF, 119 .cmd0iclkout = MT47H128M16RT25E_INVERT_CLKOUT, 120 121 .cmd1csratio = MT47H128M16RT25E_RATIO, 122 .cmd1dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF, 123 .cmd1iclkout = MT47H128M16RT25E_INVERT_CLKOUT, 124 125 .cmd2csratio = MT47H128M16RT25E_RATIO, 126 .cmd2dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF, 127 .cmd2iclkout = MT47H128M16RT25E_INVERT_CLKOUT, 128 }; 129 130 static const struct emif_regs ddr2_emif_reg_data = { 131 .sdram_config = MT47H128M16RT25E_EMIF_SDCFG, 132 .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF, 133 .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1, 134 .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2, 135 .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3, 136 .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY, 137 }; 138 139 static const struct ddr_data ddr3_data = { 140 .datardsratio0 = MT41J128MJT125_RD_DQS, 141 .datawdsratio0 = MT41J128MJT125_WR_DQS, 142 .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE, 143 .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA, 144 .datadldiff0 = PHY_DLL_LOCK_DIFF, 145 }; 146 147 static const struct ddr_data ddr3_beagleblack_data = { 148 .datardsratio0 = MT41K256M16HA125E_RD_DQS, 149 .datawdsratio0 = MT41K256M16HA125E_WR_DQS, 150 .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE, 151 .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA, 152 .datadldiff0 = PHY_DLL_LOCK_DIFF, 153 }; 154 155 static const struct ddr_data ddr3_evm_data = { 156 .datardsratio0 = MT41J512M8RH125_RD_DQS, 157 .datawdsratio0 = MT41J512M8RH125_WR_DQS, 158 .datafwsratio0 = MT41J512M8RH125_PHY_FIFO_WE, 159 .datawrsratio0 = MT41J512M8RH125_PHY_WR_DATA, 160 .datadldiff0 = PHY_DLL_LOCK_DIFF, 161 }; 162 163 static const struct cmd_control ddr3_cmd_ctrl_data = { 164 .cmd0csratio = MT41J128MJT125_RATIO, 165 .cmd0dldiff = MT41J128MJT125_DLL_LOCK_DIFF, 166 .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT, 167 168 .cmd1csratio = MT41J128MJT125_RATIO, 169 .cmd1dldiff = MT41J128MJT125_DLL_LOCK_DIFF, 170 .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT, 171 172 .cmd2csratio = MT41J128MJT125_RATIO, 173 .cmd2dldiff = MT41J128MJT125_DLL_LOCK_DIFF, 174 .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT, 175 }; 176 177 static const struct cmd_control ddr3_beagleblack_cmd_ctrl_data = { 178 .cmd0csratio = MT41K256M16HA125E_RATIO, 179 .cmd0dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF, 180 .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT, 181 182 .cmd1csratio = MT41K256M16HA125E_RATIO, 183 .cmd1dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF, 184 .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT, 185 186 .cmd2csratio = MT41K256M16HA125E_RATIO, 187 .cmd2dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF, 188 .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT, 189 }; 190 191 static const struct cmd_control ddr3_evm_cmd_ctrl_data = { 192 .cmd0csratio = MT41J512M8RH125_RATIO, 193 .cmd0dldiff = MT41J512M8RH125_DLL_LOCK_DIFF, 194 .cmd0iclkout = MT41J512M8RH125_INVERT_CLKOUT, 195 196 .cmd1csratio = MT41J512M8RH125_RATIO, 197 .cmd1dldiff = MT41J512M8RH125_DLL_LOCK_DIFF, 198 .cmd1iclkout = MT41J512M8RH125_INVERT_CLKOUT, 199 200 .cmd2csratio = MT41J512M8RH125_RATIO, 201 .cmd2dldiff = MT41J512M8RH125_DLL_LOCK_DIFF, 202 .cmd2iclkout = MT41J512M8RH125_INVERT_CLKOUT, 203 }; 204 205 static struct emif_regs ddr3_emif_reg_data = { 206 .sdram_config = MT41J128MJT125_EMIF_SDCFG, 207 .ref_ctrl = MT41J128MJT125_EMIF_SDREF, 208 .sdram_tim1 = MT41J128MJT125_EMIF_TIM1, 209 .sdram_tim2 = MT41J128MJT125_EMIF_TIM2, 210 .sdram_tim3 = MT41J128MJT125_EMIF_TIM3, 211 .zq_config = MT41J128MJT125_ZQ_CFG, 212 .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY | 213 PHY_EN_DYN_PWRDN, 214 }; 215 216 static struct emif_regs ddr3_beagleblack_emif_reg_data = { 217 .sdram_config = MT41K256M16HA125E_EMIF_SDCFG, 218 .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF, 219 .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1, 220 .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2, 221 .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3, 222 .zq_config = MT41K256M16HA125E_ZQ_CFG, 223 .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY, 224 }; 225 226 static struct emif_regs ddr3_evm_emif_reg_data = { 227 .sdram_config = MT41J512M8RH125_EMIF_SDCFG, 228 .ref_ctrl = MT41J512M8RH125_EMIF_SDREF, 229 .sdram_tim1 = MT41J512M8RH125_EMIF_TIM1, 230 .sdram_tim2 = MT41J512M8RH125_EMIF_TIM2, 231 .sdram_tim3 = MT41J512M8RH125_EMIF_TIM3, 232 .zq_config = MT41J512M8RH125_ZQ_CFG, 233 .emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY | 234 PHY_EN_DYN_PWRDN, 235 }; 236 237 #ifdef CONFIG_SPL_OS_BOOT 238 int spl_start_uboot(void) 239 { 240 /* break into full u-boot on 'c' */ 241 return (serial_tstc() && serial_getc() == 'c'); 242 } 243 #endif 244 245 #define OSC (V_OSCK/1000000) 246 const struct dpll_params dpll_ddr = { 247 266, OSC-1, 1, -1, -1, -1, -1}; 248 const struct dpll_params dpll_ddr_evm_sk = { 249 303, OSC-1, 1, -1, -1, -1, -1}; 250 const struct dpll_params dpll_ddr_bone_black = { 251 400, OSC-1, 1, -1, -1, -1, -1}; 252 253 const struct dpll_params *get_dpll_ddr_params(void) 254 { 255 struct am335x_baseboard_id header; 256 257 enable_i2c0_pin_mux(); 258 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); 259 if (read_eeprom(&header) < 0) 260 puts("Could not get board ID.\n"); 261 262 if (board_is_evm_sk(&header)) 263 return &dpll_ddr_evm_sk; 264 else if (board_is_bone_lt(&header)) 265 return &dpll_ddr_bone_black; 266 else if (board_is_evm_15_or_later(&header)) 267 return &dpll_ddr_evm_sk; 268 else 269 return &dpll_ddr; 270 } 271 272 #endif 273 274 /* 275 * early system init of muxing and clocks. 276 */ 277 void s_init(void) 278 { 279 __maybe_unused struct am335x_baseboard_id header; 280 281 /* 282 * The ROM will only have set up sufficient pinmux to allow for the 283 * first 4KiB NOR to be read, we must finish doing what we know of 284 * the NOR mux in this space in order to continue. 285 */ 286 #ifdef CONFIG_NOR_BOOT 287 asm("stmfd sp!, {r2 - r4}"); 288 asm("movw r4, #0x8A4"); 289 asm("movw r3, #0x44E1"); 290 asm("orr r4, r4, r3, lsl #16"); 291 asm("mov r2, #9"); 292 asm("mov r3, #8"); 293 asm("gpmc_mux: str r2, [r4], #4"); 294 asm("subs r3, r3, #1"); 295 asm("bne gpmc_mux"); 296 asm("ldmfd sp!, {r2 - r4}"); 297 #endif 298 299 #ifdef CONFIG_SPL_BUILD 300 /* 301 * Save the boot parameters passed from romcode. 302 * We cannot delay the saving further than this, 303 * to prevent overwrites. 304 */ 305 save_omap_boot_params(); 306 #endif 307 308 /* WDT1 is already running when the bootloader gets control 309 * Disable it to avoid "random" resets 310 */ 311 writel(0xAAAA, &wdtimer->wdtwspr); 312 while (readl(&wdtimer->wdtwwps) != 0x0) 313 ; 314 writel(0x5555, &wdtimer->wdtwspr); 315 while (readl(&wdtimer->wdtwwps) != 0x0) 316 ; 317 318 #if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT) 319 /* Setup the PLLs and the clocks for the peripherals */ 320 pll_init(); 321 322 /* Enable RTC32K clock */ 323 rtc32k_enable(); 324 325 #ifdef CONFIG_SERIAL1 326 enable_uart0_pin_mux(); 327 #endif /* CONFIG_SERIAL1 */ 328 #ifdef CONFIG_SERIAL2 329 enable_uart1_pin_mux(); 330 #endif /* CONFIG_SERIAL2 */ 331 #ifdef CONFIG_SERIAL3 332 enable_uart2_pin_mux(); 333 #endif /* CONFIG_SERIAL3 */ 334 #ifdef CONFIG_SERIAL4 335 enable_uart3_pin_mux(); 336 #endif /* CONFIG_SERIAL4 */ 337 #ifdef CONFIG_SERIAL5 338 enable_uart4_pin_mux(); 339 #endif /* CONFIG_SERIAL5 */ 340 #ifdef CONFIG_SERIAL6 341 enable_uart5_pin_mux(); 342 #endif /* CONFIG_SERIAL6 */ 343 344 uart_soft_reset(); 345 346 #if defined(CONFIG_NOR_BOOT) 347 /* We want our console now. */ 348 gd->baudrate = CONFIG_BAUDRATE; 349 serial_init(); 350 gd->have_console = 1; 351 #else 352 gd = &gdata; 353 354 preloader_console_init(); 355 #endif 356 357 /* Initalize the board header */ 358 enable_i2c0_pin_mux(); 359 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); 360 if (read_eeprom(&header) < 0) 361 puts("Could not get board ID.\n"); 362 363 enable_board_pin_mux(&header); 364 if (board_is_evm_sk(&header)) { 365 /* 366 * EVM SK 1.2A and later use gpio0_7 to enable DDR3. 367 * This is safe enough to do on older revs. 368 */ 369 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en"); 370 gpio_direction_output(GPIO_DDR_VTT_EN, 1); 371 } 372 373 if (board_is_evm_sk(&header)) 374 config_ddr(303, MT41J128MJT125_IOCTRL_VALUE, &ddr3_data, 375 &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); 376 else if (board_is_bone_lt(&header)) 377 config_ddr(400, MT41K256M16HA125E_IOCTRL_VALUE, 378 &ddr3_beagleblack_data, 379 &ddr3_beagleblack_cmd_ctrl_data, 380 &ddr3_beagleblack_emif_reg_data, 0); 381 else if (board_is_evm_15_or_later(&header)) 382 config_ddr(303, MT41J512M8RH125_IOCTRL_VALUE, &ddr3_evm_data, 383 &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0); 384 else 385 config_ddr(266, MT47H128M16RT25E_IOCTRL_VALUE, &ddr2_data, 386 &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0); 387 #endif 388 } 389 390 /* 391 * Basic board specific setup. Pinmux has been handled already. 392 */ 393 int board_init(void) 394 { 395 #ifdef CONFIG_NOR 396 const u32 gpmc_nor[GPMC_MAX_REG] = { STNOR_GPMC_CONFIG1, 397 STNOR_GPMC_CONFIG2, STNOR_GPMC_CONFIG3, STNOR_GPMC_CONFIG4, 398 STNOR_GPMC_CONFIG5, STNOR_GPMC_CONFIG6, STNOR_GPMC_CONFIG7 }; 399 #endif 400 401 gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100; 402 403 gpmc_init(); 404 405 #ifdef CONFIG_NOR 406 /* Reconfigure CS0 for NOR instead of NAND. */ 407 enable_gpmc_cs_config(gpmc_nor, &gpmc_cfg->cs[0], 408 CONFIG_SYS_FLASH_BASE, GPMC_SIZE_16M); 409 #endif 410 411 return 0; 412 } 413 414 #ifdef CONFIG_BOARD_LATE_INIT 415 int board_late_init(void) 416 { 417 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 418 char safe_string[HDR_NAME_LEN + 1]; 419 struct am335x_baseboard_id header; 420 421 if (read_eeprom(&header) < 0) 422 puts("Could not get board ID.\n"); 423 424 /* Now set variables based on the header. */ 425 strncpy(safe_string, (char *)header.name, sizeof(header.name)); 426 safe_string[sizeof(header.name)] = 0; 427 setenv("board_name", safe_string); 428 429 strncpy(safe_string, (char *)header.version, sizeof(header.version)); 430 safe_string[sizeof(header.version)] = 0; 431 setenv("board_rev", safe_string); 432 #endif 433 434 return 0; 435 } 436 #endif 437 438 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ 439 (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) 440 static void cpsw_control(int enabled) 441 { 442 /* VTP can be added here */ 443 444 return; 445 } 446 447 static struct cpsw_slave_data cpsw_slaves[] = { 448 { 449 .slave_reg_ofs = 0x208, 450 .sliver_reg_ofs = 0xd80, 451 .phy_id = 0, 452 }, 453 { 454 .slave_reg_ofs = 0x308, 455 .sliver_reg_ofs = 0xdc0, 456 .phy_id = 1, 457 }, 458 }; 459 460 static struct cpsw_platform_data cpsw_data = { 461 .mdio_base = CPSW_MDIO_BASE, 462 .cpsw_base = CPSW_BASE, 463 .mdio_div = 0xff, 464 .channels = 8, 465 .cpdma_reg_ofs = 0x800, 466 .slaves = 1, 467 .slave_data = cpsw_slaves, 468 .ale_reg_ofs = 0xd00, 469 .ale_entries = 1024, 470 .host_port_reg_ofs = 0x108, 471 .hw_stats_reg_ofs = 0x900, 472 .bd_ram_ofs = 0x2000, 473 .mac_control = (1 << 5), 474 .control = cpsw_control, 475 .host_port_num = 0, 476 .version = CPSW_CTRL_VERSION_2, 477 }; 478 #endif 479 480 #if defined(CONFIG_DRIVER_TI_CPSW) || \ 481 (defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) 482 int board_eth_init(bd_t *bis) 483 { 484 int rv, n = 0; 485 uint8_t mac_addr[6]; 486 uint32_t mac_hi, mac_lo; 487 __maybe_unused struct am335x_baseboard_id header; 488 489 /* try reading mac address from efuse */ 490 mac_lo = readl(&cdev->macid0l); 491 mac_hi = readl(&cdev->macid0h); 492 mac_addr[0] = mac_hi & 0xFF; 493 mac_addr[1] = (mac_hi & 0xFF00) >> 8; 494 mac_addr[2] = (mac_hi & 0xFF0000) >> 16; 495 mac_addr[3] = (mac_hi & 0xFF000000) >> 24; 496 mac_addr[4] = mac_lo & 0xFF; 497 mac_addr[5] = (mac_lo & 0xFF00) >> 8; 498 499 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ 500 (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) 501 if (!getenv("ethaddr")) { 502 printf("<ethaddr> not set. Validating first E-fuse MAC\n"); 503 504 if (is_valid_ether_addr(mac_addr)) 505 eth_setenv_enetaddr("ethaddr", mac_addr); 506 } 507 508 #ifdef CONFIG_DRIVER_TI_CPSW 509 if (read_eeprom(&header) < 0) 510 puts("Could not get board ID.\n"); 511 512 if (board_is_bone(&header) || board_is_bone_lt(&header) || 513 board_is_idk(&header)) { 514 writel(MII_MODE_ENABLE, &cdev->miisel); 515 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = 516 PHY_INTERFACE_MODE_MII; 517 } else { 518 writel(RGMII_MODE_ENABLE, &cdev->miisel); 519 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = 520 PHY_INTERFACE_MODE_RGMII; 521 } 522 523 rv = cpsw_register(&cpsw_data); 524 if (rv < 0) 525 printf("Error %d registering CPSW switch\n", rv); 526 else 527 n += rv; 528 #endif 529 530 /* 531 * 532 * CPSW RGMII Internal Delay Mode is not supported in all PVT 533 * operating points. So we must set the TX clock delay feature 534 * in the AR8051 PHY. Since we only support a single ethernet 535 * device in U-Boot, we only do this for the first instance. 536 */ 537 #define AR8051_PHY_DEBUG_ADDR_REG 0x1d 538 #define AR8051_PHY_DEBUG_DATA_REG 0x1e 539 #define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5 540 #define AR8051_RGMII_TX_CLK_DLY 0x100 541 542 if (board_is_evm_sk(&header) || board_is_gp_evm(&header)) { 543 const char *devname; 544 devname = miiphy_get_current_dev(); 545 546 miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_ADDR_REG, 547 AR8051_DEBUG_RGMII_CLK_DLY_REG); 548 miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_DATA_REG, 549 AR8051_RGMII_TX_CLK_DLY); 550 } 551 #endif 552 #if defined(CONFIG_USB_ETHER) && \ 553 (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT)) 554 if (is_valid_ether_addr(mac_addr)) 555 eth_setenv_enetaddr("usbnet_devaddr", mac_addr); 556 557 rv = usb_eth_initialize(bis); 558 if (rv < 0) 559 printf("Error %d registering USB_ETHER\n", rv); 560 else 561 n += rv; 562 #endif 563 return n; 564 } 565 #endif 566