1 /* 2 * ddr_defs.h 3 * 4 * ddr specific header 5 * 6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #ifndef _DDR_DEFS_H 12 #define _DDR_DEFS_H 13 14 #include <asm/arch/hardware.h> 15 #include <asm/emif.h> 16 17 /* AM335X EMIF Register values */ 18 #define VTP_CTRL_READY (0x1 << 5) 19 #define VTP_CTRL_ENABLE (0x1 << 6) 20 #define VTP_CTRL_START_EN (0x1) 21 #define PHY_DLL_LOCK_DIFF 0x0 22 #define DDR_CKE_CTRL_NORMAL 0x1 23 #define PHY_EN_DYN_PWRDN (0x1 << 20) 24 25 /* Micron MT47H128M16RT-25E */ 26 #define MT47H128M16RT25E_EMIF_READ_LATENCY 0x100005 27 #define MT47H128M16RT25E_EMIF_TIM1 0x0666B3C9 28 #define MT47H128M16RT25E_EMIF_TIM2 0x243631CA 29 #define MT47H128M16RT25E_EMIF_TIM3 0x0000033F 30 #define MT47H128M16RT25E_EMIF_SDCFG 0x41805332 31 #define MT47H128M16RT25E_EMIF_SDREF 0x0000081a 32 #define MT47H128M16RT25E_DLL_LOCK_DIFF 0x0 33 #define MT47H128M16RT25E_RATIO 0x80 34 #define MT47H128M16RT25E_INVERT_CLKOUT 0x00 35 #define MT47H128M16RT25E_RD_DQS 0x12 36 #define MT47H128M16RT25E_WR_DQS 0x00 37 #define MT47H128M16RT25E_PHY_WRLVL 0x00 38 #define MT47H128M16RT25E_PHY_GATELVL 0x00 39 #define MT47H128M16RT25E_PHY_WR_DATA 0x40 40 #define MT47H128M16RT25E_PHY_FIFO_WE 0x80 41 #define MT47H128M16RT25E_PHY_RANK0_DELAY 0x1 42 #define MT47H128M16RT25E_IOCTRL_VALUE 0x18B 43 44 /* Micron MT41J128M16JT-125 */ 45 #define MT41J128MJT125_EMIF_READ_LATENCY 0x06 46 #define MT41J128MJT125_EMIF_TIM1 0x0888A39B 47 #define MT41J128MJT125_EMIF_TIM2 0x26337FDA 48 #define MT41J128MJT125_EMIF_TIM3 0x501F830F 49 #define MT41J128MJT125_EMIF_SDCFG 0x61C04AB2 50 #define MT41J128MJT125_EMIF_SDREF 0x0000093B 51 #define MT41J128MJT125_ZQ_CFG 0x50074BE4 52 #define MT41J128MJT125_DLL_LOCK_DIFF 0x1 53 #define MT41J128MJT125_RATIO 0x40 54 #define MT41J128MJT125_INVERT_CLKOUT 0x1 55 #define MT41J128MJT125_RD_DQS 0x3B 56 #define MT41J128MJT125_WR_DQS 0x85 57 #define MT41J128MJT125_PHY_WR_DATA 0xC1 58 #define MT41J128MJT125_PHY_FIFO_WE 0x100 59 #define MT41J128MJT125_IOCTRL_VALUE 0x18B 60 61 /* Micron MT41J256M8HX-15E */ 62 #define MT41J256M8HX15E_EMIF_READ_LATENCY 0x06 63 #define MT41J256M8HX15E_EMIF_TIM1 0x0888A39B 64 #define MT41J256M8HX15E_EMIF_TIM2 0x26337FDA 65 #define MT41J256M8HX15E_EMIF_TIM3 0x501F830F 66 #define MT41J256M8HX15E_EMIF_SDCFG 0x61C04B32 67 #define MT41J256M8HX15E_EMIF_SDREF 0x0000093B 68 #define MT41J256M8HX15E_ZQ_CFG 0x50074BE4 69 #define MT41J256M8HX15E_DLL_LOCK_DIFF 0x1 70 #define MT41J256M8HX15E_RATIO 0x40 71 #define MT41J256M8HX15E_INVERT_CLKOUT 0x1 72 #define MT41J256M8HX15E_RD_DQS 0x3B 73 #define MT41J256M8HX15E_WR_DQS 0x85 74 #define MT41J256M8HX15E_PHY_WR_DATA 0xC1 75 #define MT41J256M8HX15E_PHY_FIFO_WE 0x100 76 #define MT41J256M8HX15E_IOCTRL_VALUE 0x18B 77 78 /* Micron MT41K256M16HA-125E */ 79 #define MT41K256M16HA125E_EMIF_READ_LATENCY 0x100007 80 #define MT41K256M16HA125E_EMIF_TIM1 0x0AAAD4DB 81 #define MT41K256M16HA125E_EMIF_TIM2 0x266B7FDA 82 #define MT41K256M16HA125E_EMIF_TIM3 0x501F867F 83 #define MT41K256M16HA125E_EMIF_SDCFG 0x61C05332 84 #define MT41K256M16HA125E_EMIF_SDREF 0xC30 85 #define MT41K256M16HA125E_ZQ_CFG 0x50074BE4 86 #define MT41K256M16HA125E_DLL_LOCK_DIFF 0x1 87 #define MT41K256M16HA125E_RATIO 0x80 88 #define MT41K256M16HA125E_INVERT_CLKOUT 0x0 89 #define MT41K256M16HA125E_RD_DQS 0x38 90 #define MT41K256M16HA125E_WR_DQS 0x44 91 #define MT41K256M16HA125E_PHY_WR_DATA 0x7D 92 #define MT41K256M16HA125E_PHY_FIFO_WE 0x94 93 #define MT41K256M16HA125E_IOCTRL_VALUE 0x18B 94 95 /* Micron MT41J512M8RH-125 on EVM v1.5 */ 96 #define MT41J512M8RH125_EMIF_READ_LATENCY 0x06 97 #define MT41J512M8RH125_EMIF_TIM1 0x0888A39B 98 #define MT41J512M8RH125_EMIF_TIM2 0x26517FDA 99 #define MT41J512M8RH125_EMIF_TIM3 0x501F84EF 100 #define MT41J512M8RH125_EMIF_SDCFG 0x61C04BB2 101 #define MT41J512M8RH125_EMIF_SDREF 0x0000093B 102 #define MT41J512M8RH125_ZQ_CFG 0x50074BE4 103 #define MT41J512M8RH125_DLL_LOCK_DIFF 0x1 104 #define MT41J512M8RH125_RATIO 0x80 105 #define MT41J512M8RH125_INVERT_CLKOUT 0x0 106 #define MT41J512M8RH125_RD_DQS 0x3B 107 #define MT41J512M8RH125_WR_DQS 0x3C 108 #define MT41J512M8RH125_PHY_FIFO_WE 0xA5 109 #define MT41J512M8RH125_PHY_WR_DATA 0x74 110 #define MT41J512M8RH125_IOCTRL_VALUE 0x18B 111 112 /* Samsung K4B2G1646E-BIH9 */ 113 #define K4B2G1646EBIH9_EMIF_READ_LATENCY 0x06 114 #define K4B2G1646EBIH9_EMIF_TIM1 0x0888A39B 115 #define K4B2G1646EBIH9_EMIF_TIM2 0x2A04011A 116 #define K4B2G1646EBIH9_EMIF_TIM3 0x501F820F 117 #define K4B2G1646EBIH9_EMIF_SDCFG 0x61C24AB2 118 #define K4B2G1646EBIH9_EMIF_SDREF 0x0000093B 119 #define K4B2G1646EBIH9_ZQ_CFG 0x50074BE4 120 #define K4B2G1646EBIH9_DLL_LOCK_DIFF 0x1 121 #define K4B2G1646EBIH9_RATIO 0x40 122 #define K4B2G1646EBIH9_INVERT_CLKOUT 0x1 123 #define K4B2G1646EBIH9_RD_DQS 0x3B 124 #define K4B2G1646EBIH9_WR_DQS 0x85 125 #define K4B2G1646EBIH9_PHY_FIFO_WE 0x100 126 #define K4B2G1646EBIH9_PHY_WR_DATA 0xC1 127 #define K4B2G1646EBIH9_IOCTRL_VALUE 0x18B 128 129 /** 130 * Configure DMM 131 */ 132 void config_dmm(const struct dmm_lisa_map_regs *regs); 133 134 /** 135 * Configure SDRAM 136 */ 137 void config_sdram(const struct emif_regs *regs, int nr); 138 139 /** 140 * Set SDRAM timings 141 */ 142 void set_sdram_timings(const struct emif_regs *regs, int nr); 143 144 /** 145 * Configure DDR PHY 146 */ 147 void config_ddr_phy(const struct emif_regs *regs, int nr); 148 149 void ddr_pll_config(unsigned int ddrpll_m); 150 151 struct ddr_cmd_regs { 152 unsigned int resv0[7]; 153 unsigned int cm0csratio; /* offset 0x01C */ 154 unsigned int resv1[2]; 155 unsigned int cm0dldiff; /* offset 0x028 */ 156 unsigned int cm0iclkout; /* offset 0x02C */ 157 unsigned int resv2[8]; 158 unsigned int cm1csratio; /* offset 0x050 */ 159 unsigned int resv3[2]; 160 unsigned int cm1dldiff; /* offset 0x05C */ 161 unsigned int cm1iclkout; /* offset 0x060 */ 162 unsigned int resv4[8]; 163 unsigned int cm2csratio; /* offset 0x084 */ 164 unsigned int resv5[2]; 165 unsigned int cm2dldiff; /* offset 0x090 */ 166 unsigned int cm2iclkout; /* offset 0x094 */ 167 unsigned int resv6[3]; 168 }; 169 170 struct ddr_data_regs { 171 unsigned int dt0rdsratio0; /* offset 0x0C8 */ 172 unsigned int resv1[4]; 173 unsigned int dt0wdsratio0; /* offset 0x0DC */ 174 unsigned int resv2[4]; 175 unsigned int dt0wiratio0; /* offset 0x0F0 */ 176 unsigned int resv3; 177 unsigned int dt0wimode0; /* offset 0x0F8 */ 178 unsigned int dt0giratio0; /* offset 0x0FC */ 179 unsigned int resv4; 180 unsigned int dt0gimode0; /* offset 0x104 */ 181 unsigned int dt0fwsratio0; /* offset 0x108 */ 182 unsigned int resv5[4]; 183 unsigned int dt0dqoffset; /* offset 0x11C */ 184 unsigned int dt0wrsratio0; /* offset 0x120 */ 185 unsigned int resv6[4]; 186 unsigned int dt0rdelays0; /* offset 0x134 */ 187 unsigned int dt0dldiff0; /* offset 0x138 */ 188 unsigned int resv7[12]; 189 }; 190 191 /** 192 * This structure represents the DDR registers on AM33XX devices. 193 * We make use of DDR_PHY_BASE_ADDR2 to address the DATA1 registers that 194 * correspond to DATA1 registers defined here. 195 */ 196 struct ddr_regs { 197 unsigned int resv0[7]; 198 unsigned int cm0csratio; /* offset 0x01C */ 199 unsigned int resv1[2]; 200 unsigned int cm0dldiff; /* offset 0x028 */ 201 unsigned int cm0iclkout; /* offset 0x02C */ 202 unsigned int resv2[8]; 203 unsigned int cm1csratio; /* offset 0x050 */ 204 unsigned int resv3[2]; 205 unsigned int cm1dldiff; /* offset 0x05C */ 206 unsigned int cm1iclkout; /* offset 0x060 */ 207 unsigned int resv4[8]; 208 unsigned int cm2csratio; /* offset 0x084 */ 209 unsigned int resv5[2]; 210 unsigned int cm2dldiff; /* offset 0x090 */ 211 unsigned int cm2iclkout; /* offset 0x094 */ 212 unsigned int resv6[12]; 213 unsigned int dt0rdsratio0; /* offset 0x0C8 */ 214 unsigned int resv7[4]; 215 unsigned int dt0wdsratio0; /* offset 0x0DC */ 216 unsigned int resv8[4]; 217 unsigned int dt0wiratio0; /* offset 0x0F0 */ 218 unsigned int resv9; 219 unsigned int dt0wimode0; /* offset 0x0F8 */ 220 unsigned int dt0giratio0; /* offset 0x0FC */ 221 unsigned int resv10; 222 unsigned int dt0gimode0; /* offset 0x104 */ 223 unsigned int dt0fwsratio0; /* offset 0x108 */ 224 unsigned int resv11[4]; 225 unsigned int dt0dqoffset; /* offset 0x11C */ 226 unsigned int dt0wrsratio0; /* offset 0x120 */ 227 unsigned int resv12[4]; 228 unsigned int dt0rdelays0; /* offset 0x134 */ 229 unsigned int dt0dldiff0; /* offset 0x138 */ 230 }; 231 232 /** 233 * Encapsulates DDR CMD control registers. 234 */ 235 struct cmd_control { 236 unsigned long cmd0csratio; 237 unsigned long cmd0csforce; 238 unsigned long cmd0csdelay; 239 unsigned long cmd0dldiff; 240 unsigned long cmd0iclkout; 241 unsigned long cmd1csratio; 242 unsigned long cmd1csforce; 243 unsigned long cmd1csdelay; 244 unsigned long cmd1dldiff; 245 unsigned long cmd1iclkout; 246 unsigned long cmd2csratio; 247 unsigned long cmd2csforce; 248 unsigned long cmd2csdelay; 249 unsigned long cmd2dldiff; 250 unsigned long cmd2iclkout; 251 }; 252 253 /** 254 * Encapsulates DDR DATA registers. 255 */ 256 struct ddr_data { 257 unsigned long datardsratio0; 258 unsigned long datawdsratio0; 259 unsigned long datawiratio0; 260 unsigned long datagiratio0; 261 unsigned long datafwsratio0; 262 unsigned long datawrsratio0; 263 unsigned long datauserank0delay; 264 unsigned long datadldiff0; 265 }; 266 267 /** 268 * Configure DDR CMD control registers 269 */ 270 void config_cmd_ctrl(const struct cmd_control *cmd, int nr); 271 272 /** 273 * Configure DDR DATA registers 274 */ 275 void config_ddr_data(const struct ddr_data *data, int nr); 276 277 /** 278 * This structure represents the DDR io control on AM33XX devices. 279 */ 280 struct ddr_cmdtctrl { 281 unsigned int cm0ioctl; 282 unsigned int cm1ioctl; 283 unsigned int cm2ioctl; 284 unsigned int resv2[12]; 285 unsigned int dt0ioctl; 286 unsigned int dt1ioctl; 287 }; 288 289 /** 290 * Configure DDR io control registers 291 */ 292 void config_io_ctrl(unsigned long val); 293 294 struct ddr_ctrl { 295 unsigned int ddrioctrl; 296 unsigned int resv1[325]; 297 unsigned int ddrckectrl; 298 }; 299 300 void config_ddr(unsigned int pll, unsigned int ioctrl, 301 const struct ddr_data *data, const struct cmd_control *ctrl, 302 const struct emif_regs *regs, int nr); 303 304 #endif /* _DDR_DEFS_H */ 305