| b208e3da | 15-May-2020 |
Gabriel Fernandez <gabriel.fernandez@st.com> |
refactor(st-clock): directly use oscillator name
Instead of transmitting an 'enum stm32mp_osc_id', just send
directly the clock name with a 'const char *'
Change-Id: I866b05cbb1685a9b9f80e63dcd5ba7
refactor(st-clock): directly use oscillator name
Instead of transmitting an 'enum stm32mp_osc_id', just send
directly the clock name with a 'const char *'
Change-Id: I866b05cbb1685a9b9f80e63dcd5ba7b1d35fc932
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
show more ...
|
| 31e9750b | 02-Jul-2019 |
Lionel Debieve <lionel.debieve@st.com> |
feat(st-clock): check HSE configuration in serial boot
In case of programmer mode, the bootrom manages to auto-detect
HSE clock configuration. In order to detect a bad device tree
setting in BL2, it
feat(st-clock): check HSE configuration in serial boot
In case of programmer mode, the bootrom manages to auto-detect
HSE clock configuration. In order to detect a bad device tree
setting in BL2, it will crash during programming if the configuration
is not aligned with the auto-detection.
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Change-Id: I230697695745d6282d14b1ebfa6e4c4caa0cd8e2
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|
| bcccdacc | 01-Jul-2019 |
Patrick Delaunay <patrick.delaunay@st.com> |
feat(st-clock): manage disabled oscillator
Support "disabled" status for oscillator in device tree.
At boot time, the clock tree initialization performs the following
tasks:
- enabling of the oscil
feat(st-clock): manage disabled oscillator
Support "disabled" status for oscillator in device tree.
At boot time, the clock tree initialization performs the following
tasks:
- enabling of the oscillators present in the device tree and not
disabled,
- disabling of the HSI oscillator if the node is absent or disabled
(always activated by bootROM).
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Change-Id: I176276022334f3d97ba0250b54062f0ae970e239
show more ...
|
| 964e5ff1 | 13-Nov-2019 |
Nicolas Le Bayon <nicolas.le.bayon@st.com> |
refactor(st-clock): improve DT parsing for PLL nodes
Add a function to get PLL settings from DT:
"cfg" property is mandatory, an error is generated if not found.
"frac" is optional, default value is
refactor(st-clock): improve DT parsing for PLL nodes
Add a function to get PLL settings from DT:
"cfg" property is mandatory, an error is generated if not found.
"frac" is optional, default value is returned if not found.
"csg" is optional too, a boolean value indicates if it has been
found, and its value is updated.
Store each PLL node validity information, this avoids parsing DT
several times.
Change-Id: I039466fbe1e67d160f7112814e7bb63b661804d0
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
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|
| 1c87d60b | 17-Jan-2022 |
Joanna Farley <joanna.farley@arm.com> |
Merge "feat(cpu/cortex_a53): add L1PCTL macro definiton for CPUACTLR_EL1" into integration |
| 97c91147 | 13-Jan-2022 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes from topic "st_mapping_update" into integration
* changes:
feat(stm32mp1): enable BL2_IN_XIP_MEM to remove relocation sections
refactor(stm32mp1): reduce MMU memory regions and spl
Merge changes from topic "st_mapping_update" into integration
* changes:
feat(stm32mp1): enable BL2_IN_XIP_MEM to remove relocation sections
refactor(stm32mp1): reduce MMU memory regions and split XLAT by context
feat(st): map 2MB for ROM code
fix(stm32mp1): restrict DEVICE2 mapping in BL2
show more ...
|
| 1f4adc3a | 13-Jan-2022 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes I52b241b2,I25b4b97c into integration
* changes:
feat(mt8186): add Vcore DVFS driver
feat(mt8186): add SPM suspend driver |
| 8bbb1d80 | 21-Oct-2021 |
Jiafei Pan <Jiafei.Pan@nxp.com> |
feat(cpu/cortex_a53): add L1PCTL macro definiton for CPUACTLR_EL1
Add L1PCTL field definiton in register CPUACTLR_EL1.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: Iebfb240ac58aa8f3dc8
feat(cpu/cortex_a53): add L1PCTL macro definiton for CPUACTLR_EL1
Add L1PCTL field definiton in register CPUACTLR_EL1.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: Iebfb240ac58aa8f3dc870804bf4390dfbdfa9b95
show more ...
|
| 635e6b10 | 16-Nov-2021 |
jason-ch chen <jason-ch.chen@mediatek.corp-partner.google.com> |
feat(mt8186): add Vcore DVFS driver
Add Vcore DVFS to SPM driver.
TEST=build pass
BUG=b:202871018
Signed-off-by: Jason-ch Chen <jason-ch.chen@mediatek.com>
Change-Id: I52b241b2cdb792be74390cbaa09a
feat(mt8186): add Vcore DVFS driver
Add Vcore DVFS to SPM driver.
TEST=build pass
BUG=b:202871018
Signed-off-by: Jason-ch Chen <jason-ch.chen@mediatek.com>
Change-Id: I52b241b2cdb792be74390cbaa09a728ddbe6593a
show more ...
|
| 7ac6a76c | 16-Nov-2021 |
jason-ch chen <jason-ch.chen@mediatek.corp-partner.google.com> |
feat(mt8186): add SPM suspend driver
Add SPM suspend driver for suspend/resume features.
TEST=build pass
BUG=b:202871018
Signed-off-by: Jason-ch Chen <jason-ch.chen@mediatek.com>
Change-Id: I25b4b
feat(mt8186): add SPM suspend driver
Add SPM suspend driver for suspend/resume features.
TEST=build pass
BUG=b:202871018
Signed-off-by: Jason-ch Chen <jason-ch.chen@mediatek.com>
Change-Id: I25b4b97cd3138a7b347385539e47ccfa884d64fc
show more ...
|
| 59da207e | 13-Oct-2021 |
Davidson K <davidson.kumaresan@arm.com> |
feat(tc): enable tracing
Total Compute has ETE and TRBE tracing components and they have
to be enabled to capture the execution trace of the processor.
Signed-off-by: Davidson K <davidson.kumaresan
feat(tc): enable tracing
Total Compute has ETE and TRBE tracing components and they have
to be enabled to capture the execution trace of the processor.
Signed-off-by: Davidson K <davidson.kumaresan@arm.com>
Change-Id: I3c86c11be2c655a61ecefa3eb2e4e3951577a113
show more ...
|
| d958d10e | 15-Sep-2021 |
Yann Gautier <yann.gautier@foss.st.com> |
feat(stm32mp1): enable BL2_IN_XIP_MEM to remove relocation sections
Because the BL2 is not relocated, the usage of BL2_IN_XIP_MEM
can be used. It reduces the binary size by removing all relocation
s
feat(stm32mp1): enable BL2_IN_XIP_MEM to remove relocation sections
Because the BL2 is not relocated, the usage of BL2_IN_XIP_MEM
can be used. It reduces the binary size by removing all relocation
sections. XIP will not be used when STM32MP_USE_STM32IMAGE is
defined. Introduce new definitions for SEPARATE_CODE_AND_RODATA.
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Change-Id: Ifd76f14e5bc98990bf84e0bfd4ee0b4e49a9a293
show more ...
|
| ac1b24d5 | 16-Jan-2020 |
Yann Gautier <yann.gautier@st.com> |
refactor(stm32mp1): reduce MMU memory regions and split XLAT by context
Simplify the BL2 MMU mapping and reduce the memory regions
number. Split the XLAT define between BL2 and BL32 as binaries
do n
refactor(stm32mp1): reduce MMU memory regions and split XLAT by context
Simplify the BL2 MMU mapping and reduce the memory regions
number. Split the XLAT define between BL2 and BL32 as binaries
do not share the same tables anymore.
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Change-Id: Iaf09e72b4cc29acbe376f6f1cd2a8116c793ba26
show more ...
|
| 1697ad8c | 15-Sep-2021 |
Yann Gautier <yann.gautier@foss.st.com> |
feat(st): map 2MB for ROM code
This allows reducing MMU tables, and as there is nothing after ROM code
in memory mapping, this has no impact.
Change-Id: If51facb96a523770465cb06eb1ab400f75d26db3
Si
feat(st): map 2MB for ROM code
This allows reducing MMU tables, and as there is nothing after ROM code
in memory mapping, this has no impact.
Change-Id: If51facb96a523770465cb06eb1ab400f75d26db3
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
show more ...
|
| db3e0ece | 17-Sep-2020 |
Yann Gautier <yann.gautier@st.com> |
fix(stm32mp1): restrict DEVICE2 mapping in BL2
Only NAND memory map area can be of interest for BL2 in the
DEVICE2 area. Map DEVICE2 under STM32MP_RAW_NAND flag.
Change-Id: I7e3b39579e4a2525b25cb19
fix(stm32mp1): restrict DEVICE2 mapping in BL2
Only NAND memory map area can be of interest for BL2 in the
DEVICE2 area. Map DEVICE2 under STM32MP_RAW_NAND flag.
Change-Id: I7e3b39579e4a2525b25cb1987d6ec38038d0de2b
Signed-off-by: Yann Gautier <yann.gautier@st.com>
show more ...
|
| 32d50422 | 15-Dec-2021 |
Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org> |
fix(imx8mp): change the BL31 physical load address
Change BL31 load address to 0x970000. This was done by Change-Id
I96d572fc. But then changed back to 0x960000 by Change-Id I8308c629.
However, 0x97
fix(imx8mp): change the BL31 physical load address
Change BL31 load address to 0x970000. This was done by Change-Id
I96d572fc. But then changed back to 0x960000 by Change-Id I8308c629.
However, 0x970000 is the correct value thus we change it back again.
Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
Change-Id: Ia0db4877123b89072f723d18e2bcce25ef38f47d
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|
| d52ed024 | 08-Jan-2022 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
refactor(renesas): disable CRYPTO_SUPPORT option
Disabled CRYPTO_SUPPORT option for Renesas platform as it does not
follow the TF-A authentication mechanism where Trusted-Boot mandates
Crypto module
refactor(renesas): disable CRYPTO_SUPPORT option
Disabled CRYPTO_SUPPORT option for Renesas platform as it does not
follow the TF-A authentication mechanism where Trusted-Boot mandates
Crypto module support.
Change-Id: I3aa771e983e3dde083dd8a861f25c0714ffd707f
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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|
| 88c51c3f | 08-Jan-2022 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
refactor(fvp): avoid Measured-Boot dependency on Trusted-Boot
As Measured-Boot and Trusted-Boot are orthogonal, removed
Trusted-Boot's dependency on Measured-Boot by allowing them
to apply the Crypt
refactor(fvp): avoid Measured-Boot dependency on Trusted-Boot
As Measured-Boot and Trusted-Boot are orthogonal, removed
Trusted-Boot's dependency on Measured-Boot by allowing them
to apply the Crypto module changes independently using the
CRYPTO_SUPPORT build flag.
Change-Id: I5a420e5d84f3fefe0c0092d822dab981e6390bbf
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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|
| 0aa0b3af | 16-Dec-2021 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
refactor(measured-boot): avoid Measured-Boot dependency on Trusted-Boot
Measured-Boot and Trusted-Boot are orthogonal to each other and hence
removed dependency of Trusted-Boot on Measured-Boot by m
refactor(measured-boot): avoid Measured-Boot dependency on Trusted-Boot
Measured-Boot and Trusted-Boot are orthogonal to each other and hence
removed dependency of Trusted-Boot on Measured-Boot by making below
changes -
1. BL1 and BL2 main functions are used for initializing Crypto module
instead of the authentication module
2. Updated Crypto module registration macro for MEASURED_BOOT with only
necessary callbacks for calculating image hashes
3. The 'load_auth_image' function is now used for the image measurement
during Trusted or Non-Trusted Boot flow
Change-Id: I3570e80bae8ce8f5b58d84bd955aa43e925d9fff
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
show more ...
|
| c9c56f6e | 08-Jan-2022 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
build: introduce CRYPTO_SUPPORT build option
Introduced CRYPTO_SUPPORT an internal, non-user facing
build option and set it when the TRUSTED_BOARD_BOOT or
MEASURED_BOOT option is enabled.
Change-Id
build: introduce CRYPTO_SUPPORT build option
Introduced CRYPTO_SUPPORT an internal, non-user facing
build option and set it when the TRUSTED_BOARD_BOOT or
MEASURED_BOOT option is enabled.
Change-Id: Iae723d57a755a8b534b6ced650016365c62d4e05
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
show more ...
|
| e537bcde | 10-Jan-2022 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "feat(mt8195): apply erratas of CA78 for MT8195" into integration |
| 5cc20229 | 01-Dec-2021 |
Chris Kay <chris.kay@arm.com> |
style(commitlint): reorder header/body max line length fields
This change simply reorders the `body-max-line-length` and
`header-max-line-length` fields to be in the order that most people
mentally
style(commitlint): reorder header/body max line length fields
This change simply reorders the `body-max-line-length` and
`header-max-line-length` fields to be in the order that most people
mentally expect. This has no actual function impact.
Change-Id: Ice0db951e4049baaf4de9372255407adc4e3bf66
Signed-off-by: Chris Kay <chris.kay@arm.com>
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|
| 8edd19e4 | 01-Dec-2021 |
Chris Kay <chris.kay@arm.com> |
chore(npm): update package versions/license
These fields were not updated accidentally on the v2.6.0 release.
Change-Id: I215105da618ff6f72057eaa40a34ff4b24f7ee36
Signed-off-by: Chris Kay <chris.ka
chore(npm): update package versions/license
These fields were not updated accidentally on the v2.6.0 release.
Change-Id: I215105da618ff6f72057eaa40a34ff4b24f7ee36
Signed-off-by: Chris Kay <chris.kay@arm.com>
show more ...
|
| f7a92518 | 07-Jan-2022 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "st_ddr_updates" into integration
* changes:
refactor(st-ddr): move basic tests in a dedicated file
refactor(st-ddr): reorganize generic and specific elements
feat(stm
Merge changes from topic "st_ddr_updates" into integration
* changes:
refactor(st-ddr): move basic tests in a dedicated file
refactor(st-ddr): reorganize generic and specific elements
feat(stm32mp1): allow configuration of DDR AXI ports number
refactor(st-ddr): update parameter array initialization
feat(st-ddr): add read valid training support
refactor(stm32mp1): remove the support of calibration result
fix(st-ddr): correct DDR warnings
show more ...
|
| 32de790f | 07-Jan-2022 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "fix(st): manage UART clock and reset only in BL2" into integration |