build(intel): define a macro for SIMICS build

SIMICS builds have different UART configurations compared
to hardware build. Hence, this patch defines a macro to
differentiate between both.

Signed-of

build(intel): define a macro for SIMICS build

SIMICS builds have different UART configurations compared
to hardware build. Hence, this patch defines a macro to
differentiate between both.

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: Iadecd5445e06611486ac3c6a214a6d0dc8ccd27b

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build(intel): add N5X as a new Intel platform

This commit adds a new Intel platform called N5X.
This preliminary patch only have Bl31 support.

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muh

build(intel): add N5X as a new Intel platform

This commit adds a new Intel platform called N5X.
This preliminary patch only have Bl31 support.

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: Ib31f9c4a5a0dabdce81c1d5b0d4776188add7195

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build(intel): initial commit for crypto driver

This patch adds driver for Intel FPGA's Crypto Services.
These services are provided by Intel platform
Secure Device Manager(SDM) and are made accessib

build(intel): initial commit for crypto driver

This patch adds driver for Intel FPGA's Crypto Services.
These services are provided by Intel platform
Secure Device Manager(SDM) and are made accessible by
processor components (ie ATF).
Below is the list of enabled features:
- Send SDM certificates
- Efuse provision data dump
- Encryption/decryption service
- Hardware IP random number generator

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: If7604cd1cacf27a38a9a29ec6b85b07385e1ea26

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Merge "fix(errata): workaround for Cortex-A710 2282622" into integration

fix(errata): workaround for Cortex-A710 2282622

Cortex-A710 erratum 2282622 is a Cat B erratum that applies to revisions
r0p0, r1p0, and r2p0, and is fixed in r2p1. The workaround is to set
CPUACTL

fix(errata): workaround for Cortex-A710 2282622

Cortex-A710 erratum 2282622 is a Cat B erratum that applies to revisions
r0p0, r1p0, and r2p0, and is fixed in r2p1. The workaround is to set
CPUACTLR2_EL1[0] to 1, which will force PLDW/PFRM ST to behave like
PLD/PRFM LD and not cause invalidations to other PE caches.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775101

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Ic48409822536e9eacc003300036a1f0489593020

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Merge "docs(security): security advisory for CVE-2022-23960" into integration

docs(security): security advisory for CVE-2022-23960

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I17b0847ff71e4a291bf7ba41fd71fe08c400b5e8

Merge changes I18d47384,Icc3c7424,I73f20d82,I07325644,Iff10ad26, ... into integration

* changes:
fix(zynqmp): query node status to power up APU
feat(zynqmp): pm_api_clock_get_num_clocks cleanup

Merge changes I18d47384,Icc3c7424,I73f20d82,I07325644,Iff10ad26, ... into integration

* changes:
fix(zynqmp): query node status to power up APU
feat(zynqmp): pm_api_clock_get_num_clocks cleanup
feat(zynqmp): add feature check support
fix(zynqmp): use common interface for eemi apis
feat(zynqmp): add support to get info of xilfpga
feat(zynqmp): pass ioctl calls to firmware

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Merge "fix(st-pmic): add static const to pmic_ops" into integration

fix(st-pmic): add static const to pmic_ops

The static was found by sparse tool:
drivers/st/pmic/stm32mp_pmic.c:456:18: warning: symbol 'pmic_ops'
was not declared. Should it be static?
The const wa

fix(st-pmic): add static const to pmic_ops

The static was found by sparse tool:
drivers/st/pmic/stm32mp_pmic.c:456:18: warning: symbol 'pmic_ops'
was not declared. Should it be static?
The const was also missing.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: Ibb5cfaf67ac980bf0af27712a95dbef05b617c25

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Merge "refactor(mbedtls): allow platform to specify their config file" into integration

Merge "docs(maintainers): add maintained files for MediaTek SoCs" into integration

Merge "fix(versal): fix the incorrect log message" into integration

fix(versal): fix the incorrect log message

When the atf-handoff-params are updated we are returning
FSBL_HANDOFF_SUCCESS, but the return condition is wrongly
updated and added a error log which is i

fix(versal): fix the incorrect log message

When the atf-handoff-params are updated we are returning
FSBL_HANDOFF_SUCCESS, but the return condition is wrongly
updated and added a error log which is incorrect.
Fixing the incorrect log message.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I44ebbb861831b86afcb87f09ddb2e23614393c28

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Merge "fix(st-clock): initialize pllcfg table" into integration

Merge changes from topic "st-uart-baudrate" into integration

* changes:
refactor(st): configure UART baudrate
docs(stm32mp1): document some compilation flags
feat(st-uart): manage oversampling

Merge changes from topic "st-uart-baudrate" into integration

* changes:
refactor(st): configure UART baudrate
docs(stm32mp1): document some compilation flags
feat(st-uart): manage oversampling by 8
fix(st-uart): correctly fill BRR register

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refactor(st): configure UART baudrate

Add the possibility to configure console UART baudrate, it can be passed
as a command line parameter with STM32MP_UART_BAUDRATE. The default value
remains 11520

refactor(st): configure UART baudrate

Add the possibility to configure console UART baudrate, it can be passed
as a command line parameter with STM32MP_UART_BAUDRATE. The default value
remains 115200.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I000df70c10b2b4dac1449556596f9820c36cf243

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docs(stm32mp1): document some compilation flags

Add missing serial boot devices flags.
Add optional compilation flags, and their defauld values.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Ch

docs(stm32mp1): document some compilation flags

Add missing serial boot devices flags.
Add optional compilation flags, and their defauld values.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I507f7110bcd7b9af136a6fc6b8af342b084c8dbc

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feat(st-uart): manage oversampling by 8

UART oversampling by 8 allows higher baud rates for UART. This is
required when (UART freq / baudrate) <= 16. In this case the OVER8 bit
needs to be enabled i

feat(st-uart): manage oversampling by 8

UART oversampling by 8 allows higher baud rates for UART. This is
required when (UART freq / baudrate) <= 16. In this case the OVER8 bit
needs to be enabled in CR1 register. And the BRR register management is
different:
USARTDIV = (2 * UART freq / baudrate) (with div round nearest)
BRR[15:4] = USARTDIV[15:4]
BRR[3] = 0
BRR[2:0] = USARTDIV[3:0] >> 1

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: Ia3fbeeb73a36a4dc485c7ba428c531e65b6f6c09

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fix(st-uart): correctly fill BRR register

To get the nearest divisor for BRR register, we use:
Divisor = (Uart clock + (baudrate / 2)) / baudrate
But lsl was wrongly used instead of lsr to have the

fix(st-uart): correctly fill BRR register

To get the nearest divisor for BRR register, we use:
Divisor = (Uart clock + (baudrate / 2)) / baudrate
But lsl was wrongly used instead of lsr to have the division by 2.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: Iedcc3ccdb4cf8268012e82a66df2a9ec48fc1d79

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fix(st-clock): initialize pllcfg table

The issue was found by Coverity:
CID 376582: (UNINIT)
Using uninitialized value "*pllcfg[_PLL4]" when calling
"stm32mp1_check_pll_conf".
CID 376582:

fix(st-clock): initialize pllcfg table

The issue was found by Coverity:
CID 376582: (UNINIT)
Using uninitialized value "*pllcfg[_PLL4]" when calling
"stm32mp1_check_pll_conf".
CID 376582: (UNINIT)
Using uninitialized value "*pllcfg[_PLL3]" when calling
"stm32mp1_check_pll_conf".

Check PLL configs are valid before using pllcfg.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I49de849eaf451d0c165a8eb8555112a0a4140bbc

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Merge "feat(ff-a): forward FFA_VERSION from SPMD to SPMC" into integration

docs(maintainers): add maintained files for MediaTek SoCs

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I2d71b2fef2f2aee507a6e7c4b9b9d8175446a0ca

Merge "feat(mt8186): disable 26MHz clock while suspending" into integration

fix(zynqmp): query node status to power up APU

If APU is in suspending state and if wakeup request comes then
PMUFW returns error which is not handled at ATF side.

To fix this, get the APU node sta

fix(zynqmp): query node status to power up APU

If APU is in suspending state and if wakeup request comes then
PMUFW returns error which is not handled at ATF side.

To fix this, get the APU node status before calling wakeup and
return error if found in suspending state.

Here, we can not handle the error code of pm_req_wakeup() from PMUFW
because ATF is already calling pm_client_wakeup() before calling
pm_req_wakeup().

Signed-off-by: Ravi Patel <ravi.patel@xilinx.com>
Signed-off-by: Ronak Jain <ronak.jain@xilinx.com>
Change-Id: I18d47384e46e22ae49e804093ad0641b7a6349e2

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