1 /* 2 * Copyright (c) 2020-2022, Intel Corporation. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <arch.h> 9 #include <arch_helpers.h> 10 #include <common/bl_common.h> 11 #include <drivers/arm/gicv2.h> 12 #include <drivers/ti/uart/uart_16550.h> 13 #include <lib/mmio.h> 14 #include <lib/xlat_tables/xlat_tables.h> 15 16 #include "socfpga_mailbox.h" 17 #include "socfpga_private.h" 18 19 static entry_point_info_t bl32_image_ep_info; 20 static entry_point_info_t bl33_image_ep_info; 21 22 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 23 { 24 entry_point_info_t *next_image_info; 25 26 next_image_info = (type == NON_SECURE) ? 27 &bl33_image_ep_info : &bl32_image_ep_info; 28 29 /* None of the images on this platform can have 0x0 as the entrypoint */ 30 if (next_image_info->pc) { 31 return next_image_info; 32 } else { 33 return NULL; 34 } 35 } 36 37 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 38 u_register_t arg2, u_register_t arg3) 39 { 40 static console_t console; 41 42 mmio_write_64(PLAT_SEC_ENTRY, 0); 43 44 console_16550_register(PLAT_UART0_BASE, PLAT_UART_CLOCK, PLAT_BAUDRATE, 45 &console); 46 /* 47 * Check params passed from BL31 should not be NULL, 48 */ 49 void *from_bl2 = (void *) arg0; 50 51 bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2; 52 53 assert(params_from_bl2 != NULL); 54 55 /* 56 * Copy BL32 (if populated by BL31) and BL33 entry point information. 57 * They are stored in Secure RAM, in BL31's address space. 58 */ 59 60 if (params_from_bl2->h.type == PARAM_BL_PARAMS && 61 params_from_bl2->h.version >= VERSION_2) { 62 63 bl_params_node_t *bl_params = params_from_bl2->head; 64 65 while (bl_params != NULL) { 66 if (bl_params->image_id == BL33_IMAGE_ID) 67 bl33_image_ep_info = *bl_params->ep_info; 68 69 bl_params = bl_params->next_params_info; 70 } 71 } else { 72 struct socfpga_bl31_params *arg_from_bl2 = 73 (struct socfpga_bl31_params *) from_bl2; 74 75 assert(arg_from_bl2->h.type == PARAM_BL31); 76 assert(arg_from_bl2->h.version >= VERSION_1); 77 78 bl32_image_ep_info = *arg_from_bl2->bl32_ep_info; 79 bl33_image_ep_info = *arg_from_bl2->bl33_ep_info; 80 } 81 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 82 } 83 84 static const interrupt_prop_t s10_interrupt_props[] = { 85 PLAT_INTEL_SOCFPGA_G1S_IRQ_PROPS(GICV2_INTR_GROUP0), 86 PLAT_INTEL_SOCFPGA_G0_IRQ_PROPS(GICV2_INTR_GROUP0) 87 }; 88 89 static unsigned int target_mask_array[PLATFORM_CORE_COUNT]; 90 91 static const gicv2_driver_data_t plat_gicv2_gic_data = { 92 .gicd_base = PLAT_INTEL_SOCFPGA_GICD_BASE, 93 .gicc_base = PLAT_INTEL_SOCFPGA_GICC_BASE, 94 .interrupt_props = s10_interrupt_props, 95 .interrupt_props_num = ARRAY_SIZE(s10_interrupt_props), 96 .target_masks = target_mask_array, 97 .target_masks_num = ARRAY_SIZE(target_mask_array), 98 }; 99 100 /******************************************************************************* 101 * Perform any BL3-1 platform setup code 102 ******************************************************************************/ 103 void bl31_platform_setup(void) 104 { 105 socfpga_delay_timer_init(); 106 107 /* Initialize the gic cpu and distributor interfaces */ 108 gicv2_driver_init(&plat_gicv2_gic_data); 109 gicv2_distif_init(); 110 gicv2_pcpu_distif_init(); 111 gicv2_cpuif_enable(); 112 113 /* Signal secondary CPUs to jump to BL31 (BL2 = U-boot SPL) */ 114 mmio_write_64(PLAT_CPU_RELEASE_ADDR, 115 (uint64_t)plat_secondary_cpus_bl31_entry); 116 117 mailbox_hps_stage_notify(HPS_EXECUTION_STATE_SSBL); 118 } 119 120 const mmap_region_t plat_dm_mmap[] = { 121 MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE, 122 MT_MEMORY | MT_RW | MT_NS), 123 MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE, 124 MT_DEVICE | MT_RW | MT_NS), 125 MAP_REGION_FLAT(DEVICE2_BASE, DEVICE2_SIZE, 126 MT_DEVICE | MT_RW | MT_SECURE), 127 MAP_REGION_FLAT(OCRAM_BASE, OCRAM_SIZE, 128 MT_NON_CACHEABLE | MT_RW | MT_SECURE), 129 MAP_REGION_FLAT(DEVICE3_BASE, DEVICE3_SIZE, 130 MT_DEVICE | MT_RW | MT_SECURE), 131 MAP_REGION_FLAT(MEM64_BASE, MEM64_SIZE, 132 MT_DEVICE | MT_RW | MT_NS), 133 MAP_REGION_FLAT(DEVICE4_BASE, DEVICE4_SIZE, 134 MT_DEVICE | MT_RW | MT_NS), 135 {0} 136 }; 137 138 /******************************************************************************* 139 * Perform the very early platform specific architectural setup here. At the 140 * moment this is only intializes the mmu in a quick and dirty way. 141 ******************************************************************************/ 142 void bl31_plat_arch_setup(void) 143 { 144 const mmap_region_t bl_regions[] = { 145 MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE, 146 MT_MEMORY | MT_RW | MT_SECURE), 147 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, 148 MT_CODE | MT_SECURE), 149 MAP_REGION_FLAT(BL_RO_DATA_BASE, 150 BL_RO_DATA_END - BL_RO_DATA_BASE, 151 MT_RO_DATA | MT_SECURE), 152 #if USE_COHERENT_MEM 153 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, 154 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, 155 MT_DEVICE | MT_RW | MT_SECURE), 156 #endif 157 {0} 158 }; 159 160 setup_page_tables(bl_regions, plat_dm_mmap); 161 enable_mmu_el3(0); 162 } 163