Merge changes Ie650728a,Ie2736ef4 into integration

* changes:
refactor(stm32mp1-fdts): add missing spaces for consistent codestyle
refactor(stm32mp1-fdts): drop unused DDR calibration result on

Merge changes Ie650728a,Ie2736ef4 into integration

* changes:
refactor(stm32mp1-fdts): add missing spaces for consistent codestyle
refactor(stm32mp1-fdts): drop unused DDR calibration result on DHCOM

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Merge "docs(prerequisites): fix "Build Host" title" into integration

docs(prerequisites): fix "Build Host" title

Add an empty line just before the "Build Host" title.

Without this, the title is not properly recognized, it does not get
added to the table of contents

docs(prerequisites): fix "Build Host" title

Add an empty line just before the "Build Host" title.

Without this, the title is not properly recognized, it does not get
added to the table of contents and the underlining characters appear
as dashes, as can be seen here:

https://trustedfirmware-a.readthedocs.io/en/v2.7/getting_started/prerequisites.html#prerequisites

Change-Id: Ia89cf3de0588495cbe64b0247dc860619f5ea6a8
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

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Merge "fix(cpus): workaround for Neoverse-N2 erratum 2388450" into integration

Merge "feat(cpus): add a64fx cpu to tf-a" into integration

feat(sve): support full SVE vector length

Currently the SVE code hard codes a maximum vector length of 512 bits
when configuring SVE rather than the architecture supported maximum.
While this is fin

feat(sve): support full SVE vector length

Currently the SVE code hard codes a maximum vector length of 512 bits
when configuring SVE rather than the architecture supported maximum.
While this is fine for current physical implementations the architecture
allows for vector lengths up to 2048 bits and emulated implementations
generally allow any length up to this maximum.

Since there may be system specific reasons to limit the maximum vector
length make the limit configurable, defaulting to the architecture
maximum. The default should be suitable for most implementations since
the hardware will limit the actual vector length selected to what is
physically supported in the system.

Signed-off-by: Mark Brown <broonie@kernel.org>
Change-Id: I22c32c98a81c0cf9562411189d8a610a5b61ca12

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build(changelog): add stm32mp13 and stm32mp15 fdts scopes

Some fdts changes in STM32MP1 family can be dedicated to one SoC,
STM32MP13 or STM32MP15. Add the dedicated scopes.

Signed-off-by: Yann Gau

build(changelog): add stm32mp13 and stm32mp15 fdts scopes

Some fdts changes in STM32MP1 family can be dedicated to one SoC,
STM32MP13 or STM32MP15. Add the dedicated scopes.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I2d64244054251c1f89dfe1ebbf6ce9dac21d47b6

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Merge changes Iec22dcab,Ib88b4b5d,I50cd6b82,If1167785,I9b3a08ef, ... into integration

* changes:
feat(imx8m): keep pu domains in default state during boot stage
feat(imx8m): add the PU power dom

Merge changes Iec22dcab,Ib88b4b5d,I50cd6b82,If1167785,I9b3a08ef, ... into integration

* changes:
feat(imx8m): keep pu domains in default state during boot stage
feat(imx8m): add the PU power domain support on imx8mm/mn
feat(imx8m): add the anamix pll override setting
feat(imx8m): add the ddr frequency change support for imx8m family
feat(imx8mn): enable dram retention suuport on imx8mn
feat(imx8mm): enable dram retention suuport on imx8mm
feat(imx8m): add dram retention flow for imx8m family

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refactor(stm32mp1-fdts): add missing spaces for consistent codestyle

Change-Id: Ie650728a0c671f553679b050afd969ce604ca111
Signed-off-by: Johann Neuhauser <jneuhauser@dh-electronics.com>

refactor(stm32mp1-fdts): drop unused DDR calibration result on DHCOM

Change-Id: Ie2736ef4c463c51d109c13e59f541fe65039d7c6
Signed-off-by: Johann Neuhauser <jneuhauser@dh-electronics.com>

Merge "feat(stm32mp15-fdts): add support for STM32MP157C based DHCOM SoM on PDK2 board" into integration

feat(stm32mp15-fdts): add support for STM32MP157C based DHCOM SoM on PDK2 board

This is an SoM in SODIMM-200 format on an evaluation board called
"DHCOM Premium Developer Kit #2" (DHCOM PDK2 for sho

feat(stm32mp15-fdts): add support for STM32MP157C based DHCOM SoM on PDK2 board

This is an SoM in SODIMM-200 format on an evaluation board called
"DHCOM Premium Developer Kit #2" (DHCOM PDK2 for short). The SoM features an
STM32MP157C SoC with 1 GB DDR3, 8 GB eMMC, microSD and 2 MB SPI flash.
The baseboard has multiple UART, USB, SPI, and I2C ports/headers and several
other interfaces that are not important for TF-A.

These dts(i) files are based on DHCOM dt's from Linux 5.16 and U-Boot 2022.01.
The DRAM calibration values are taken from U-Boot 2022.01 and are optimized for
industrial temperature range above 85° C.

TF-A on this board was fully tested with the latest OP-TEE developer setup.

Change-Id: I696c01742954d761fbad312cd1059e3ab01fa93c
Signed-off-by: Johann Neuhauser <jneuhauser@dh-electronics.com>

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Merge "feat(libfdt): add function to set MAC addresses" into integration

Merge "refactor(arm): add debug logs to show the reason behind skipping firmware config loading" into integration

refactor(arm): add debug logs to show the reason behind skipping firmware config loading

Added debug logs to show the reason behind skipping firmware
configuration loading, and also a few debug stri

refactor(arm): add debug logs to show the reason behind skipping firmware config loading

Added debug logs to show the reason behind skipping firmware
configuration loading, and also a few debug strings were corrected.
Additionally, a panic will be triggered if the configuration sanity
fails.

Change-Id: I6bbd67b72801e178a14cbe677a8831b25a907d0c
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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fix(ufs): add retries to ufs_read_capacity

This change replaces the polling loop with fixed number of retries,
returns error values and handles them in ufs_enum.

Signed-off-by: Rohit Ner <rohitner@

fix(ufs): add retries to ufs_read_capacity

This change replaces the polling loop with fixed number of retries,
returns error values and handles them in ufs_enum.

Signed-off-by: Rohit Ner <rohitner@google.com>
Change-Id: Ia769ef26703c7525091e55ff46aaae4637db933c

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fix(cpus): workaround for Neoverse-N2 erratum 2388450

Neoverse-N2 erratum 2388450 is a cat B erratum that applies to
revision r0p0 and is fixed in r0p1. The workaround is to set
bit[40] of CPUACTLR2

fix(cpus): workaround for Neoverse-N2 erratum 2388450

Neoverse-N2 erratum 2388450 is a cat B erratum that applies to
revision r0p0 and is fixed in r0p1. The workaround is to set
bit[40] of CPUACTLR2_EL1 to disable folding of demand requests into
older prefetches with L2 miss requests outstanding.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1982442/latest

Change-Id: I6dd949c79cea8dbad322e569aa5de86cf8cf9639
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>

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Merge "fix(morello): move BL31 to run from DRAM space" into integration

Merge changes from topic "sgi-updates-jul-2022" into integration

* changes:
feat(sgi): bump bl1 rw size
refactor(sgi): rewrite address space size definitions

Merge "feat(zynqmp): resolve the misra 10.1 warnings" into integration

feat(sgi): bump bl1 rw size

Increase BL1 RW size by 16 KiB to accommodate for future development.

Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Change-Id: I21626a97de

feat(sgi): bump bl1 rw size

Increase BL1 RW size by 16 KiB to accommodate for future development.

Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Change-Id: I21626a97de4a6c98c25b93b9f79e16325c6e4349

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refactor(sgi): rewrite address space size definitions

The value of the macro CSS_SGI_REMOTE_CHIP_MEM_OFFSET can be different
across all the Neoverse reference design platforms. This value depends
on

refactor(sgi): rewrite address space size definitions

The value of the macro CSS_SGI_REMOTE_CHIP_MEM_OFFSET can be different
across all the Neoverse reference design platforms. This value depends
on the number of address bits used per chip. So let all platforms define
CSS_SGI_ADDR_BITS_PER_CHIP which specifies the number of address bits
used per chip.

In addition to this, reuse the definition of CSS_SGI_ADDR_BITS_PER_CHIP
for single chip platforms and CSS_SGI_REMOTE_CHIP_MEM_OFFSET for multi-
chip platforms to determine the maximum address space size. Also,
increase the RD-N2 multi-chip address space per chip from 4TB to 64TB.

Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Change-Id: If5e69ec26c2389304c71911729d4addbdf8b2686

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fix(morello): move BL31 to run from DRAM space

The EL3 runtime firmware has been running from internal trusted
SRAM space on the Morello platform. Due to unavailability of tag
support for the intern

fix(morello): move BL31 to run from DRAM space

The EL3 runtime firmware has been running from internal trusted
SRAM space on the Morello platform. Due to unavailability of tag
support for the internal trusted SRAM this becomes a problem if
we enable capability pointers in BL31.

To support capability pointers in BL31 it has to be run from the
main DDR memory space. This patch updates the Morello platform
configuration such that BL31 is loaded and run from DDR space.

Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>
Change-Id: I16d4d757fb6f58c364f5133236d50fc06845e0b4

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Merge "fix(rme): xlat table setup fails for bl2" into integration

fix(rme): xlat table setup fails for bl2

The patch 8c980a4 created a 4KB shared region from the 32MB
Realm region for RMM-EL3 communication. But this meant that BL2
needs to map a region of 32MB - 4

fix(rme): xlat table setup fails for bl2

The patch 8c980a4 created a 4KB shared region from the 32MB
Realm region for RMM-EL3 communication. But this meant that BL2
needs to map a region of 32MB - 4KB, which required more xlat
tables at runtime. This patch maps the entire 32MB region in BL2
which is more memory efficient in terms of xlat tables needed.

Signed-off-by: Soby Mathew <soby.mathew@arm.com>
Change-Id: I17aa27545293d7b5bbec1c9132ea2c22bf2e7e65

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