1 /* 2 * Copyright (c) 2022, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2021-2022, Xilinx, Inc. All rights reserved. 4 * Copyright (C) 2022, Advanced Micro Devices, Inc. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #ifndef VERSAL_NET_DEF_H 10 #define VERSAL_NET_DEF_H 11 12 #include <plat/arm/common/smccc_def.h> 13 #include <plat/common/common_def.h> 14 15 /* This part is taken from U-Boot project under GPL that's why dual license above */ 16 #define __bf_shf(x) (__builtin_ffsll(x) - 1U) 17 #define FIELD_GET(_mask, _reg) \ 18 ({ \ 19 (typeof(_mask))(((_reg) & (_mask)) >> __bf_shf(_mask)); \ 20 }) 21 22 /* List all consoles */ 23 #define VERSAL_NET_CONSOLE_ID_pl011 U(1) 24 #define VERSAL_NET_CONSOLE_ID_pl011_0 U(1) 25 #define VERSAL_NET_CONSOLE_ID_pl011_1 U(2) 26 27 #define VERSAL_NET_CONSOLE_IS(con) (VERSAL_NET_CONSOLE_ID_ ## con == VERSAL_NET_CONSOLE) 28 29 /* List all platforms */ 30 #define VERSAL_NET_SILICON U(0) 31 #define VERSAL_NET_SPP U(1) 32 #define VERSAL_NET_EMU U(2) 33 #define VERSAL_NET_QEMU U(3) 34 35 /* For platform detection */ 36 #define PMC_TAP U(0xF11A0000) 37 #define PMC_TAP_VERSION (PMC_TAP + 0x4U) 38 # define PLATFORM_MASK GENMASK(27U, 24U) 39 # define PLATFORM_VERSION_MASK GENMASK(31U, 28U) 40 41 /* Global timer reset */ 42 #define PSX_CRF U(0xEC200000) 43 #define ACPU0_CLK_CTRL U(0x10C) 44 #define ACPU_CLK_CTRL_CLKACT BIT(25) 45 46 #define RST_APU0_OFFSET U(0x300) 47 #define RST_APU_COLD_RESET BIT(0) 48 #define RST_APU_WARN_RESET BIT(4) 49 #define RST_APU_CLUSTER_COLD_RESET BIT(8) 50 #define RST_APU_CLUSTER_WARM_RESET BIT(9) 51 52 #define PSX_CRF_RST_TIMESTAMP_OFFSET U(0x33C) 53 54 #define APU_PCLI U(0xECB10000) 55 #define APU_PCLI_CPU_STEP U(0x30) 56 #define APU_PCLI_CLUSTER_CPU_STEP (4U * APU_PCLI_CPU_STEP) 57 #define APU_PCLI_CLUSTER_OFFSET U(0x8000) 58 #define APU_PCLI_CLUSTER_STEP U(0x1000) 59 #define PCLI_PREQ_OFFSET U(0x4) 60 #define PREQ_CHANGE_REQUEST BIT(0) 61 #define PCLI_PSTATE_OFFSET U(0x8) 62 #define PCLI_PSTATE_VAL_SET U(0x48) 63 #define PCLI_PSTATE_VAL_CLEAR U(0x38) 64 65 /* Firmware Image Package */ 66 #define VERSAL_NET_PRIMARY_CPU U(0) 67 68 /******************************************************************************* 69 * memory map related constants 70 ******************************************************************************/ 71 /* IPP 1.2/SPP 0.9 mapping */ 72 #define DEVICE0_BASE U(0xE8000000) /* psx, crl, iou */ 73 #define DEVICE0_SIZE U(0x08000000) 74 #define DEVICE1_BASE U(0xE2000000) /* gic */ 75 #define DEVICE1_SIZE U(0x00800000) 76 #define DEVICE2_BASE U(0xF1000000) /* uart, pmc_tap */ 77 #define DEVICE2_SIZE U(0x01000000) 78 #define CRF_BASE U(0xFD1A0000) 79 #define CRF_SIZE U(0x00600000) 80 81 /* CRL */ 82 #define VERSAL_NET_CRL U(0xEB5E0000) 83 #define VERSAL_NET_CRL_TIMESTAMP_REF_CTRL_OFFSET U(0x14C) 84 #define VERSAL_NET_CRL_RST_TIMESTAMP_OFFSET U(0x348) 85 86 #define VERSAL_NET_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT (1U << 25U) 87 88 /* IOU SCNTRS */ 89 #define VERSAL_NET_IOU_SCNTRS U(0xEC920000) 90 #define VERSAL_NET_IOU_SCNTRS_COUNTER_CONTROL_REG_OFFSET U(0) 91 #define VERSAL_NET_IOU_SCNTRS_BASE_FREQ_OFFSET U(0x20) 92 93 #define VERSAL_NET_IOU_SCNTRS_CONTROL_EN U(1) 94 95 #define APU_CLUSTER0 U(0xECC00000) 96 #define APU_RVBAR_L_0 U(0x40) 97 #define APU_RVBAR_H_0 U(0x44) 98 #define APU_CLUSTER_STEP U(0x100000) 99 100 #define SLCR_OSPI_QSPI_IOU_AXI_MUX_SEL U(0xF1060504) 101 102 /******************************************************************************* 103 * IRQ constants 104 ******************************************************************************/ 105 #define VERSAL_NET_IRQ_SEC_PHY_TIMER U(29) 106 107 /******************************************************************************* 108 * UART related constants 109 ******************************************************************************/ 110 #define VERSAL_NET_UART0_BASE U(0xF1920000) 111 #define VERSAL_NET_UART_BAUDRATE 115200 112 113 #define VERSAL_NET_UART_BASE VERSAL_NET_UART0_BASE 114 115 #define PLAT_VERSAL_NET_CRASH_UART_BASE VERSAL_NET_UART_BASE 116 #define PLAT_VERSAL_NET_CRASH_UART_CLK_IN_HZ VERSAL_NET_UART_CLOCK 117 #define VERSAL_NET_CONSOLE_BAUDRATE VERSAL_NET_UART_BAUDRATE 118 119 #endif /* VERSAL_NET_DEF_H */ 120