1 /* 2 * Copyright (c) 2021-2022, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. 4 * Copyright (C) 2022, Advanced Micro Devices, Inc. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #include <common/debug.h> 10 #include <common/runtime_svc.h> 11 #include <drivers/generic_delay_timer.h> 12 #include <lib/mmio.h> 13 #include <lib/xlat_tables/xlat_tables_v2.h> 14 #include <plat/common/platform.h> 15 16 #include <plat_private.h> 17 #include <versal_net_def.h> 18 19 uint32_t platform_id, platform_version; 20 21 /* 22 * Table of regions to map using the MMU. 23 * This doesn't include TZRAM as the 'mem_layout' argument passed to 24 * configure_mmu_elx() will give the available subset of that, 25 */ 26 const mmap_region_t plat_versal_net_mmap[] = { 27 MAP_REGION_FLAT(DEVICE0_BASE, DEVICE0_SIZE, MT_DEVICE | MT_RW | MT_SECURE), 28 MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE, MT_DEVICE | MT_RW | MT_SECURE), 29 MAP_REGION_FLAT(DEVICE2_BASE, DEVICE2_SIZE, MT_DEVICE | MT_RW | MT_SECURE), 30 MAP_REGION_FLAT(CRF_BASE, CRF_SIZE, MT_DEVICE | MT_RW | MT_SECURE), 31 { 0 } 32 }; 33 34 const mmap_region_t *plat_versal_net_get_mmap(void) 35 { 36 return plat_versal_net_mmap; 37 } 38 39 /* For saving cpu clock for certain platform */ 40 uint32_t cpu_clock; 41 42 char *board_name_decode(void) 43 { 44 switch (platform_id) { 45 case VERSAL_NET_SPP: 46 return "IPP"; 47 case VERSAL_NET_EMU: 48 return "EMU"; 49 case VERSAL_NET_SILICON: 50 return "Silicon"; 51 case VERSAL_NET_QEMU: 52 return "QEMU"; 53 default: 54 return "Unknown"; 55 } 56 } 57 58 void board_detection(void) 59 { 60 uint32_t version; 61 62 version = mmio_read_32(PMC_TAP_VERSION); 63 platform_id = FIELD_GET(PLATFORM_MASK, version); 64 platform_version = FIELD_GET(PLATFORM_VERSION_MASK, version); 65 66 if ((platform_id == VERSAL_NET_SPP) || 67 (platform_id == VERSAL_NET_EMU) || 68 (platform_id == VERSAL_NET_QEMU)) { 69 /* 70 * 9 is diff for 71 * 0 means 0.9 version 72 * 1 means 1.0 version 73 * 2 means 1.1 version 74 * etc, 75 */ 76 platform_version += 9U; 77 } 78 79 /* Make sure that console is setup to see this message */ 80 VERBOSE("Platform id: %d version: %d.%d\n", platform_id, 81 platform_version / 10U, platform_version % 10U); 82 } 83 84 void versal_net_config_setup(void) 85 { 86 uint32_t val; 87 uintptr_t crl_base, iou_scntrs_base, psx_base; 88 89 crl_base = VERSAL_NET_CRL; 90 iou_scntrs_base = VERSAL_NET_IOU_SCNTRS; 91 psx_base = PSX_CRF; 92 93 /* Reset for system timestamp generator in FPX */ 94 mmio_write_32(psx_base + PSX_CRF_RST_TIMESTAMP_OFFSET, 0); 95 96 /* Global timer init - Program time stamp reference clk */ 97 val = mmio_read_32(crl_base + VERSAL_NET_CRL_TIMESTAMP_REF_CTRL_OFFSET); 98 val |= VERSAL_NET_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT; 99 mmio_write_32(crl_base + VERSAL_NET_CRL_TIMESTAMP_REF_CTRL_OFFSET, val); 100 101 /* Clear reset of timestamp reg */ 102 mmio_write_32(crl_base + VERSAL_NET_CRL_RST_TIMESTAMP_OFFSET, 0); 103 104 /* Program freq register in System counter and enable system counter. */ 105 mmio_write_32(iou_scntrs_base + VERSAL_NET_IOU_SCNTRS_BASE_FREQ_OFFSET, 106 cpu_clock); 107 mmio_write_32(iou_scntrs_base + VERSAL_NET_IOU_SCNTRS_COUNTER_CONTROL_REG_OFFSET, 108 VERSAL_NET_IOU_SCNTRS_CONTROL_EN); 109 110 generic_delay_timer_init(); 111 } 112 113 uint32_t plat_get_syscnt_freq2(void) 114 { 115 return cpu_clock; 116 } 117