feat(cpufeat): extend check_feature() to deal with min/max

So far the check_feature() function compares the subfield of a CPU ID
register against 0, to learn if a feature is enabled or not.
This is

feat(cpufeat): extend check_feature() to deal with min/max

So far the check_feature() function compares the subfield of a CPU ID
register against 0, to learn if a feature is enabled or not.
This is problematic for checks that require a certain revision of a
feature, so we should check against a minimum version number instead.
On top of that we might need to add code to support newer versions of a
feature, so we should be alerted if new hardware introduces a higher
number.

Extend the check_feature() function to take two extra arguments: the
minimum version, and the greatest currently known number.
Then make sure that the CPU ID field is in this range.

Change-Id: I425b68535a2ba9eafd31854e74d142183b521cd5
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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refactor(cpufeat): wrap CPU ID register field isolation

Some MISRA test complains about our code to isolate CPU ID register
fields: the ID registers (and associated masks) are 64 bits wide, but
the

refactor(cpufeat): wrap CPU ID register field isolation

Some MISRA test complains about our code to isolate CPU ID register
fields: the ID registers (and associated masks) are 64 bits wide, but
the eventual field is always 4 bits wide only, so we use an unsigned
int to represent that. MISRA dislikes the differing width here.

Since the code to extract a feature field from a CPU ID register is very
schematic already, provide a wrapper macro to make this more readable,
and do the proper casting in one central place on the way.

While at it, use the same macro for the AArch32 feature detection side.

Change-Id: Ie102a9e7007a386f5879ec65e159ff041504a4ee
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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Merge changes I960771e6,I291dc627,I57f31664 into integration

* changes:
fix(ufs): set the PRDT length field properly
fix(ufs): flush the entire PRDT
fix(ufs): only allow using one slot

Merge changes from topic "mbedtls3_support" into integration

* changes:
feat(stm32mp1): add mbedtls-3.3 support config
refactor(fvp): minor cleanup with TRUSTED_BOARD_BOOT
style(crypto): add b

Merge changes from topic "mbedtls3_support" into integration

* changes:
feat(stm32mp1): add mbedtls-3.3 support config
refactor(fvp): minor cleanup with TRUSTED_BOARD_BOOT
style(crypto): add braces for if statement
feat(fvp): increase BL1_RW and BL2 size
feat(mbedtls): add support for mbedtls-3.3
refactor(crypto): avoid using struct mbedtls_pk_rsassa_pss_options
refactor(mbedtls): avoid including MBEDTLS_CONFIG_FILE

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fix(docs): add plantuml as a dependency

This wasn't listed on the web interface configuration. Perhaps it came
preloaded. Anyway, it's needed for diagrams. Add it back.

Signed-off-by: Boyan Karatot

fix(docs): add plantuml as a dependency

This wasn't listed on the web interface configuration. Perhaps it came
preloaded. Anyway, it's needed for diagrams. Add it back.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I20c1eb0e8d5abaa3533169dd9704cbd3b0eb06a5

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Merge "revert(zynqmp): remove EM SMC handler" into integration

feat(stm32mp1): add mbedtls-3.3 support config

Add stm32mp1_mbedtls_config-3.h config file for stm32mp1 builds with
mbedtls-3.3

Change-Id: I4581cb0ea7b2c7022e71aefd7ff05ee3a72f5883
Signed-off-by: G

feat(stm32mp1): add mbedtls-3.3 support config

Add stm32mp1_mbedtls_config-3.h config file for stm32mp1 builds with
mbedtls-3.3

Change-Id: I4581cb0ea7b2c7022e71aefd7ff05ee3a72f5883
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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revert(zynqmp): remove EM SMC handler

EM support was out of SMC SIP range that's why has been moved to SIP
range 0x3000 by commit acbae3998bd8 ("fix(zynqmp): move EM SMC range
to SIP range").
But af

revert(zynqmp): remove EM SMC handler

EM support was out of SMC SIP range that's why has been moved to SIP
range 0x3000 by commit acbae3998bd8 ("fix(zynqmp): move EM SMC range
to SIP range").
But after another investigation was found that this interface has no
user in any our SW and likely never adopted by anybody else. That's
why simply remove it. If there is any user it can be added back but
as TF-A size is challenging removing unused code is very welcome.
Origin code was added by commit 504925f99da0 ("xilinx: zynqmp: Add
support for Error Management").

Change-Id: I2d9222d7dde507400893e06f7f12e1713ce6bc9a
Signed-off-by: Michal Simek <michal.simek@amd.com>

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fix(imx8m): fix the dfiphymaster setting after dvfs

the dfi phy master setting need to be save/restore to make
sure it aligned with the initial config.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
R

fix(imx8m): fix the dfiphymaster setting after dvfs

the dfi phy master setting need to be save/restore to make
sure it aligned with the initial config.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <anson.huang@nxp.com>
Change-Id: I4f572b9aff9cc47a6c28524ce0fe03cdc66b88a1

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feat(imx8m): update the ddr4 dvfs flow to include ddr3l support

the DDR3L & DDR4 can share same piece of code for DDR frequency scaling.
So update the ddr4 dvfs flow to support DDR3L too.

Signed-of

feat(imx8m): update the ddr4 dvfs flow to include ddr3l support

the DDR3L & DDR4 can share same piece of code for DDR frequency scaling.
So update the ddr4 dvfs flow to support DDR3L too.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <anson.huang@nxp.com>
Change-Id: Ifc6981f05ed8a4e399adad97690197a9680f554d

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fix(imx8m): correct the rank info get fro mstr

the bitfield of active_ranks in MSTR is defined as below.
Correct the rank num get in dram_info.

0x01: one rank;
0x11: two rank;

Signed-off-by: J

fix(imx8m): correct the rank info get fro mstr

the bitfield of active_ranks in MSTR is defined as below.
Correct the rank num get in dram_info.

0x01: one rank;
0x11: two rank;

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <anson.huang@nxp.com>
Change-Id: Idcadb39f492a8fe81c973ac4136d9a1eaa32f54b

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feat(imx8m): fix the ddr4 dvfs random hang on imx8m

Remove the while loop waiting in step12 to align with what
we did before, just use a 'if' condition check for debug
purpose.

Tested-by: Peng Fan

feat(imx8m): fix the ddr4 dvfs random hang on imx8m

Remove the while loop waiting in step12 to align with what
we did before, just use a 'if' condition check for debug
purpose.

Tested-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: Id2685c5f628270a24944470d675a5c8706f39f13

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fix(ufs): set the PRDT length field properly

The PRDT length field contains the count of the entries in the PRDT. See
JEDEC Standard No. 223E, section 6.1.1, "UTP Transfer Request
Descriptor," page

fix(ufs): set the PRDT length field properly

The PRDT length field contains the count of the entries in the PRDT. See
JEDEC Standard No. 223E, section 6.1.1, "UTP Transfer Request
Descriptor," page 66. Previously we were setting the PRDT length field
to the number of bytes in the PRDT divided by four (the size in units of
32 bits). This was incorrect according to the spec.

Signed-off-by: Jorge Troncoso <jatron@google.com>
Change-Id: I960771e6ce57002872392993042fae9ec505447e

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fix(ufs): flush the entire PRDT

Previously, if the image being read exceeded 12,800 KB (or 50 PRDT
entries of size 256 KB), the UFS driver would not flush the entire
Physical Region Descriptor Table

fix(ufs): flush the entire PRDT

Previously, if the image being read exceeded 12,800 KB (or 50 PRDT
entries of size 256 KB), the UFS driver would not flush the entire
Physical Region Descriptor Table (PRDT). This would cause the UFS host
controller to read empty PRDT entries, which eventually would make the
system crash. This change updates the UFS driver to flush the entire
PRDT, irrespective of the size of the image being read.

This change also throws an error if the memory allocated for UFS
descriptors is not sufficient to hold the entire Physical Region
Descriptor Table (PRDT).

Signed-off-by: Jorge Troncoso <jatron@google.com>
Change-Id: I291dc62748992481be3cc156ce1474a6e3990ea9

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fix(ufs): only allow using one slot

Currently the UFS driver places the Command UPIU, Response UPIU, and
PRDT immediately after the UTP Transfer Request Descriptor. This space
would normally be rese

fix(ufs): only allow using one slot

Currently the UFS driver places the Command UPIU, Response UPIU, and
PRDT immediately after the UTP Transfer Request Descriptor. This space
would normally be reserved for other slots in the UTP Transfer Request
List, but because we always use slot zero, the other slots in the UTP
Transfer Request List are never used and this is okay.

Because the Command UPIU, Response UPIU, and PRDT are placed inside the
UTP Transfer Request List, the UFS driver would break if two or more
slots were used at the same time. Therefore, in a sense the
get_empty_slot() function is misleading. It gives developers the
illusion that they can use two or more slots simultaneously but in
reality they cannot.

This change deletes the get_empty_slot() function and replaces it with
is_slot_available() so that only one slot can be used.

Signed-off-by: Jorge Troncoso <jatron@google.com>
Change-Id: I57f316640a1cdd56493505ede61f3012ceb2f305

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Merge "feat(zynqmp): add hooks for mmap and early setup" into integration

fix(rme): update sample platform attestation token

Update FVP platform attestation token to comply with RMM Beta0
specification. The changes are:
- change platform implementation id claim value from

fix(rme): update sample platform attestation token

Update FVP platform attestation token to comply with RMM Beta0
specification. The changes are:
- change platform implementation id claim value from 64 to 32 bits
- change Realm Challenge
- update Hash Algorithm Identifier claim value
- add protected header
- change signing algotithm to ECDSA ES384

Change-Id: I1c5907d1a4961ce08a1408d25128de125b3f2e7f
Signed-off-by: Mate Toth-Pal <mate.toth-pal@arm.com>

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Merge "feat(build): allow additional CFLAGS for library build" into integration

feat(zynqmp): add hooks for mmap and early setup

Add early setup hooks (via custom_early_setup()) and provide a way
to cover custom memory mapping which includes extending memory map
via custom_mmap

feat(zynqmp): add hooks for mmap and early setup

Add early setup hooks (via custom_early_setup()) and provide a way
to cover custom memory mapping which includes extending memory map
via custom_mmap_add().

This likely also require to align MAX_XLAT_TABLE, MAX_XLAT_TABLES
macros. It can be done for example by defining these macros in
custom_pkg.mk
MAX_MMAP_REGIONS := XY
$(eval $(call add_define,MAX_MMAP_REGIONS))
MAX_XLAT_TABLES := XZ
$(eval $(call add_define,MAX_XLAT_TABLES))

custom_early_setup() can be used for early low level operations
related to setting up the system to correct state.

Signed-off-by: Amit Nagal <amit.nagal@amd.com>
Change-Id: I61df6f9ba5af0bc97c430974fb10a2edde44f23d

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Merge changes from topic "panic_cleanup" into integration

* changes:
refactor(bl31): use elx_panic for sysreg_handler64
refactor(aarch64): rename do_panic and el3_panic
refactor(aarch64): remo

Merge changes from topic "panic_cleanup" into integration

* changes:
refactor(bl31): use elx_panic for sysreg_handler64
refactor(aarch64): rename do_panic and el3_panic
refactor(aarch64): remove weak links to el3_panic
refactor(aarch64): refactor usage of elx_panic
refactor(aarch64): cleanup HANDLE_EA_EL3_FIRST_NS usage

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Merge "fix: remove useless "return" at void functions" into integration

Merge "fix(zynqmp): add bitmask for get_op_char API" into integration

refactor(bl31): use elx_panic for sysreg_handler64

When we reach sysreg_handler64 from any trap handling we are entering
this path from lower EL and thus we should be calling lower_el_panic
reportin

refactor(bl31): use elx_panic for sysreg_handler64

When we reach sysreg_handler64 from any trap handling we are entering
this path from lower EL and thus we should be calling lower_el_panic
reporting mechanism to print panic report.

Make report_elx_panic available through assembly func elx_panic which
could be used for reporting any lower_el_panic.

Change-Id: Ieb260cf20ea327a59db84198b2c6a6bfc9ca9537
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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Merge "docs: add interrupts-target field to sp manifest" into integration

fix(zynqmp): add bitmask for get_op_char API

As per the current functionality, there are a couple of types like
PM_OPCHAR_TYPE_TEMP, PM_OPCHAR_TYPE_POWER and PM_OPCHAR_TYPE_LATENCY
for the PM_GET_OP

fix(zynqmp): add bitmask for get_op_char API

As per the current functionality, there are a couple of types like
PM_OPCHAR_TYPE_TEMP, PM_OPCHAR_TYPE_POWER and PM_OPCHAR_TYPE_LATENCY
for the PM_GET_OP_CHARACTERISTIC EEMI API which is mismatched across
the Versal and ZynqMP platforms.

So added the bitmask functionality for PM_GET_OP_CHARACTERISTIC API
in feature check in the firmware and as part of that the firmware fill
up payload[1] with the bitmask value of supported types of the
PM_GET_OP_CHARACTERISTIC EEMI API but from TF-A based on the current
codebase it is just returning the version. So filling up the bitmask
buffer which is received from the firmware and returned the same to
the user.

Signed-off-by: Ronak Jain <ronak.jain@amd.com>
Change-Id: I2c55f3e902a5f89eed899e99a97ad9b3f0a12796

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