1 /* 2 * Copyright 2018-2023 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <drivers/delay_timer.h> 8 #include <lib/mmio.h> 9 10 #include <dram.h> 11 12 void ddr4_mr_write(uint32_t mr, uint32_t data, uint32_t mr_type, uint32_t rank) 13 { 14 uint32_t val, mr_mirror, data_mirror; 15 16 /* 17 * 1. Poll MRSTAT.mr_wr_busy until it is 0 to make sure 18 * that there is no outstanding MR transAction. 19 */ 20 while (mmio_read_32(DDRC_MRSTAT(0)) & 0x1) { 21 ; 22 } 23 24 /* 25 * 2. Write the MRCTRL0.mr_type, MRCTRL0.mr_addr, MRCTRL0.mr_rank 26 * and (for MRWs) MRCTRL1.mr_data to define the MR transaction. 27 */ 28 val = mmio_read_32(DDRC_DIMMCTL(0)); 29 if ((val & 0x2) && (rank == 0x2)) { 30 mr_mirror = (mr & 0x4) | ((mr & 0x1) << 1) | ((mr & 0x2) >> 1); /* BA0, BA1 swap */ 31 data_mirror = (data & 0x1607) | ((data & 0x8) << 1) | ((data & 0x10) >> 1) | 32 ((data & 0x20) << 1) | ((data & 0x40) >> 1) | ((data & 0x80) << 1) | 33 ((data & 0x100) >> 1) | ((data & 0x800) << 2) | ((data & 0x2000) >> 2) ; 34 } else { 35 mr_mirror = mr; 36 data_mirror = data; 37 } 38 39 mmio_write_32(DDRC_MRCTRL0(0), mr_type | (mr_mirror << 12) | (rank << 4)); 40 mmio_write_32(DDRC_MRCTRL1(0), data_mirror); 41 42 /* 43 * 3. In a separate APB transaction, write the MRCTRL0.mr_wr to 1. 44 * This bit is self-clearing, and triggers the MR transaction. 45 * The uMCTL2 then asserts the MRSTAT.mr_wr_busy while it performs 46 * the MR transaction to SDRAM, and no further accesses can be 47 * initiated until it is deasserted. 48 */ 49 mmio_setbits_32(DDRC_MRCTRL0(0), BIT(31)); 50 51 while (mmio_read_32(DDRC_MRSTAT(0))) { 52 ; 53 } 54 } 55 56 void dram_cfg_all_mr(struct dram_info *info, uint32_t pstate) 57 { 58 uint32_t num_rank = info->num_rank; 59 /* 60 * 15. Perform MRS commands as required to re-program 61 * timing registers in the SDRAM for the new frequency 62 * (in particular, CL, CWL and WR may need to be changed). 63 */ 64 65 for (int i = 1; i <= num_rank; i++) { 66 for (int j = 0; j < 6; j++) { 67 ddr4_mr_write(j, info->mr_table[pstate][j], 0, i); 68 } 69 ddr4_mr_write(6, info->mr_table[pstate][7], 0, i); 70 } 71 } 72 73 void sw_pstate(uint32_t pstate, uint32_t drate) 74 { 75 uint32_t val; 76 77 mmio_write_32(DDRC_SWCTL(0), 0x0); 78 79 /* 80 * Update any registers which may be required to 81 * change for the new frequency. 82 */ 83 mmio_write_32(DDRC_MSTR2(0), pstate); 84 mmio_setbits_32(DDRC_MSTR(0), (0x1 << 29)); 85 86 /* 87 * Toggle RFSHCTL3.refresh_update_level to allow the 88 * new refresh-related register values to propagate 89 * to the refresh logic. 90 */ 91 val = mmio_read_32(DDRC_RFSHCTL3(0)); 92 if (val & 0x2) { 93 mmio_write_32(DDRC_RFSHCTL3(0), val & 0xFFFFFFFD); 94 } else { 95 mmio_write_32(DDRC_RFSHCTL3(0), val | 0x2); 96 } 97 98 /* 99 * 19. If required, trigger the initialization in the PHY. 100 * If using the gen2 multiPHY, PLL initialization should 101 * be triggered at this point. See the PHY databook for 102 * details about the frequency change procedure. 103 */ 104 mmio_write_32(DDRC_DFIMISC(0), 0x00000000 | (pstate << 8)); 105 mmio_write_32(DDRC_DFIMISC(0), 0x00000020 | (pstate << 8)); 106 107 /* wait DFISTAT.dfi_init_complete to 0 */ 108 while (mmio_read_32(DDRC_DFISTAT(0)) & 0x1) { 109 ; 110 } 111 112 /* change the clock to the target frequency */ 113 dram_clock_switch(drate, false); 114 115 mmio_write_32(DDRC_DFIMISC(0), 0x00000000 | (pstate << 8)); 116 117 /* wait DFISTAT.dfi_init_complete to 1 */ 118 while (!(mmio_read_32(DDRC_DFISTAT(0)) & 0x1)) { 119 ; 120 } 121 122 /* 123 * When changing frequencies the controller may violate the JEDEC 124 * requirement that no more than 16 refreshes should be issued within 125 * 2*tREFI. These extra refreshes are not expected to cause a problem 126 * in the SDRAM. This issue can be avoided by waiting for at least 2*tREFI 127 * before exiting self-refresh in step 19. 128 */ 129 udelay(14); 130 131 /* 14. Exit the self-refresh state by setting PWRCTL.selfref_sw = 0. */ 132 mmio_clrbits_32(DDRC_PWRCTL(0), (1 << 5)); 133 134 while ((mmio_read_32(DDRC_STAT(0)) & 0x3f) == 0x23) { 135 ; 136 } 137 } 138 139 void ddr4_swffc(struct dram_info *info, unsigned int pstate) 140 { 141 uint32_t drate = info->timing_info->fsp_table[pstate]; 142 143 /* 144 * 1. set SWCTL.sw_done to disable quasi-dynamic register 145 * programming outside reset. 146 */ 147 mmio_write_32(DDRC_SWCTL(0), 0x0); 148 149 /* 150 * 2. Write 0 to PCTRL_n.port_en. This blocks AXI port(s) 151 * from taking any transaction (blocks traffic on AXI ports). 152 */ 153 mmio_write_32(DDRC_PCTRL_0(0), 0x0); 154 155 /* 156 * 3. Poll PSTAT.rd_port_busy_n=0 and PSTAT.wr_port_busy_n=0. 157 * Wait until all AXI ports are idle (the uMCTL2 core has to 158 * be idle). 159 */ 160 while (mmio_read_32(DDRC_PSTAT(0)) & 0x10001) { 161 ; 162 } 163 164 /* 165 * 4. Write 0 to SBRCTL.scrub_en. Disable SBR, required only if 166 * SBR instantiated. 167 * 5. Poll SBRSTAT.scrub_busy=0. 168 * 6. Set DERATEEN.derate_enable = 0, if DERATEEN.derate_eanble = 1 169 * and the read latency (RL) value needs to change after the frequency 170 * change (LPDDR2/3/4 only). 171 * 7. Set DBG1.dis_hif=1 so that no new commands will be accepted by the uMCTL2. 172 */ 173 mmio_setbits_32(DDRC_DBG1(0), (0x1 << 1)); 174 175 /* 176 * 8. Poll DBGCAM.dbg_wr_q_empty and DBGCAM.dbg_rd_q_empty to ensure 177 * that write and read data buffers are empty. 178 */ 179 while ((mmio_read_32(DDRC_DBGCAM(0)) & 0x06000000) != 0x06000000) { 180 ; 181 } 182 183 /* 184 * 9. For DDR4, update MR6 with the new tDLLK value via the Mode 185 * Register Write signals 186 * 10. Set DFILPCFG0.dfi_lp_en_sr = 0, if DFILPCFG0.dfi_lp_en_sr = 1, 187 * and wait until DFISTAT.dfi_lp_ack 188 * 11. If DFI PHY Master interface is active in uMCTL2, then disable it 189 * 12. Wait until STAT.operating_mode[1:0]!=11 indicating that the 190 * controller is not in self-refresh mode. 191 */ 192 if ((mmio_read_32(DDRC_STAT(0)) & 0x3) == 0x3) { 193 VERBOSE("DRAM is in Self Refresh\n"); 194 } 195 196 /* 197 * 13. Assert PWRCTL.selfref_sw for the DWC_ddr_umctl2 core to enter 198 * the self-refresh mode. 199 */ 200 mmio_setbits_32(DDRC_PWRCTL(0), (1 << 5)); 201 202 /* 203 * 14. Wait until STAT.operating_mode[1:0]==11 indicating that the 204 * controller core is in self-refresh mode. 205 */ 206 while ((mmio_read_32(DDRC_STAT(0)) & 0x3f) != 0x23) { 207 ; 208 } 209 210 sw_pstate(pstate, drate); 211 dram_cfg_all_mr(info, pstate); 212 213 /* 23. Enable HIF commands by setting DBG1.dis_hif=0. */ 214 mmio_clrbits_32(DDRC_DBG1(0), (0x1 << 1)); 215 216 /* 217 * 24. Reset DERATEEN.derate_enable = 1 if DERATEEN.derate_enable 218 * has been set to 0 in step 6. 219 * 25. If DFI PHY Master interface was active before step 11 then 220 * enable it back by programming DFIPHYMSTR.phymstr_en = 1'b1. 221 * 26. Write 1 to PCTRL_n.port_en. AXI port(s) are no longer blocked 222 * from taking transactions (Re-enable traffic on AXI ports) 223 */ 224 mmio_write_32(DDRC_PCTRL_0(0), 0x1); 225 226 /* 227 * 27. Write 1 to SBRCTL.scrub_en. Enable SBR if desired, only 228 * required if SBR instantiated. 229 */ 230 231 /* 232 * set SWCTL.sw_done to enable quasi-dynamic register programming 233 * outside reset. 234 */ 235 mmio_write_32(DDRC_SWCTL(0), 0x1); 236 237 /* wait SWSTAT.sw_done_ack to 1 */ 238 while (!(mmio_read_32(DDRC_SWSTAT(0)) & 0x1)) { 239 ; 240 } 241 } 242