1 /* 2 * Copyright 2018-2023 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <lib/mmio.h> 8 9 #include <dram.h> 10 11 static void lpddr4_mr_write(uint32_t mr_rank, uint32_t mr_addr, uint32_t mr_data) 12 { 13 /* 14 * 1. Poll MRSTAT.mr_wr_busy until it is 0. This checks that there 15 * is no outstanding MR transaction. No 16 * writes should be performed to MRCTRL0 and MRCTRL1 if MRSTAT.mr_wr_busy = 1. 17 */ 18 while (mmio_read_32(DDRC_MRSTAT(0)) & 0x1) 19 ; 20 21 /* 22 * 2. Write the MRCTRL0.mr_type, MRCTRL0.mr_addr, 23 * MRCTRL0.mr_rank and (for MRWs) 24 * MRCTRL1.mr_data to define the MR transaction. 25 */ 26 mmio_write_32(DDRC_MRCTRL0(0), (mr_rank << 4)); 27 mmio_write_32(DDRC_MRCTRL1(0), (mr_addr << 8) | mr_data); 28 mmio_setbits_32(DDRC_MRCTRL0(0), BIT(31)); 29 } 30 31 void lpddr4_swffc(struct dram_info *info, unsigned int init_fsp, 32 unsigned int fsp_index) 33 34 { 35 uint32_t mr, emr, emr2, emr3; 36 uint32_t mr11, mr12, mr22, mr14; 37 uint32_t val; 38 uint32_t derate_backup[3]; 39 uint32_t (*mr_data)[8]; 40 uint32_t phy_master; 41 42 /* 1. program targetd UMCTL2_REGS_FREQ1/2/3,already done, skip it. */ 43 44 /* 2. MR13.FSP-WR=1, MRW to update MR registers */ 45 mr_data = info->mr_table; 46 mr = mr_data[fsp_index][0]; 47 emr = mr_data[fsp_index][1]; 48 emr2 = mr_data[fsp_index][2]; 49 emr3 = mr_data[fsp_index][3]; 50 mr11 = mr_data[fsp_index][4]; 51 mr12 = mr_data[fsp_index][5]; 52 mr22 = mr_data[fsp_index][6]; 53 mr14 = mr_data[fsp_index][7]; 54 55 val = (init_fsp == 1) ? 0x2 << 6 : 0x1 << 6; 56 emr3 = (emr3 & 0x003f) | val | 0x0d00; 57 58 /* 12. set PWRCTL.selfref_en=0 */ 59 mmio_clrbits_32(DDRC_PWRCTL(0), 0xf); 60 61 phy_master = mmio_read_32(DDRC_DFIPHYMSTR(0)); 62 63 /* It is more safe to config it here */ 64 mmio_clrbits_32(DDRC_DFIPHYMSTR(0), 0x1); 65 66 lpddr4_mr_write(3, 13, emr3); 67 lpddr4_mr_write(3, 1, mr); 68 lpddr4_mr_write(3, 2, emr); 69 lpddr4_mr_write(3, 3, emr2); 70 lpddr4_mr_write(3, 11, mr11); 71 lpddr4_mr_write(3, 12, mr12); 72 lpddr4_mr_write(3, 14, mr14); 73 lpddr4_mr_write(3, 22, mr22); 74 75 do { 76 val = mmio_read_32(DDRC_MRSTAT(0)); 77 } while (val & 0x1); 78 79 /* 3. disable AXI ports */ 80 mmio_write_32(DDRC_PCTRL_0(0), 0x0); 81 82 /* 4.Poll PSTAT.rd_port_busy_n=0 and PSTAT.wr_port_busy_n=0. */ 83 do { 84 val = mmio_read_32(DDRC_PSTAT(0)); 85 } while (val != 0); 86 87 /* 6.disable SBRCTL.scrub_en, skip if never enable it */ 88 /* 7.poll SBRSTAT.scrub_busy Q2: should skip phy master if never enable it */ 89 /* Disable phy master */ 90 #ifdef DFILP_SPT 91 /* 8. disable DFI LP */ 92 /* DFILPCFG0.dfi_lp_en_sr */ 93 val = mmio_read_32(DDRC_DFILPCFG0(0)); 94 if (val & 0x100) { 95 mmio_write_32(DDRC_DFILPCFG0(0), 0x0); 96 do { 97 val = mmio_read_32(DDRC_DFISTAT(0)); // dfi_lp_ack 98 val2 = mmio_read_32(DDRC_STAT(0)); // operating_mode 99 } while (((val & 0x2) == 0x2) && ((val2 & 0x7) == 3)); 100 } 101 #endif 102 /* 9. wait until in normal or power down states */ 103 do { 104 /* operating_mode */ 105 val = mmio_read_32(DDRC_STAT(0)); 106 } while (((val & 0x7) != 1) && ((val & 0x7) != 2)); 107 108 /* 10. Disable automatic derating: derate_enable */ 109 val = mmio_read_32(DDRC_DERATEEN(0)); 110 derate_backup[0] = val; 111 mmio_clrbits_32(DDRC_DERATEEN(0), 0x1); 112 113 val = mmio_read_32(DDRC_FREQ1_DERATEEN(0)); 114 derate_backup[1] = val; 115 mmio_clrbits_32(DDRC_FREQ1_DERATEEN(0), 0x1); 116 117 val = mmio_read_32(DDRC_FREQ2_DERATEEN(0)); 118 derate_backup[2] = val; 119 mmio_clrbits_32(DDRC_FREQ2_DERATEEN(0), 0x1); 120 121 /* 11. disable automatic ZQ calibration */ 122 mmio_setbits_32(DDRC_ZQCTL0(0), BIT(31)); 123 mmio_setbits_32(DDRC_FREQ1_ZQCTL0(0), BIT(31)); 124 mmio_setbits_32(DDRC_FREQ2_ZQCTL0(0), BIT(31)); 125 126 /* 12. set PWRCTL.selfref_en=0 */ 127 mmio_clrbits_32(DDRC_PWRCTL(0), 0x1); 128 129 /* 13.Poll STAT.operating_mode is in "Normal" (001) or "Power-down" (010) */ 130 do { 131 val = mmio_read_32(DDRC_STAT(0)); 132 } while (((val & 0x7) != 1) && ((val & 0x7) != 2)); 133 134 /* 14-15. trigger SW SR */ 135 /* bit 5: selfref_sw, bit 6: stay_in_selfref */ 136 mmio_setbits_32(DDRC_PWRCTL(0), 0x60); 137 138 /* 16. Poll STAT.selfref_state in "Self Refresh 1" */ 139 do { 140 val = mmio_read_32(DDRC_STAT(0)); 141 } while ((val & 0x300) != 0x100); 142 143 /* 17. disable dq */ 144 mmio_setbits_32(DDRC_DBG1(0), 0x1); 145 146 /* 18. Poll DBGCAM.wr_data_pipeline_empty and DBGCAM.rd_data_pipeline_empty */ 147 do { 148 val = mmio_read_32(DDRC_DBGCAM(0)); 149 val &= 0x30000000; 150 } while (val != 0x30000000); 151 152 /* 19. change MR13.FSP-OP to new FSP and MR13.VRCG to high current */ 153 emr3 = (((~init_fsp) & 0x1) << 7) | (0x1 << 3) | (emr3 & 0x0077) | 0x0d00; 154 lpddr4_mr_write(3, 13, emr3); 155 156 /* 20. enter SR Power Down */ 157 mmio_clrsetbits_32(DDRC_PWRCTL(0), 0x60, 0x20); 158 159 /* 21. Poll STAT.selfref_state is in "SR Power down" */ 160 do { 161 val = mmio_read_32(DDRC_STAT(0)); 162 } while ((val & 0x300) != 0x200); 163 164 /* 22. set dfi_init_complete_en = 0 */ 165 166 /* 23. switch clock */ 167 /* set SWCTL.dw_done to 0 */ 168 mmio_write_32(DDRC_SWCTL(0), 0x0000); 169 170 /* 24. program frequency mode=1(bit 29), target_frequency=target_freq (bit 29) */ 171 mmio_write_32(DDRC_MSTR2(0), fsp_index); 172 173 /* 25. DBICTL for FSP-OP[1], skip it if never enable it */ 174 175 /* 26.trigger initialization in the PHY */ 176 177 /* Q3: if refresh level is updated, then should program */ 178 /* as updating refresh, need to toggle refresh_update_level signal */ 179 val = mmio_read_32(DDRC_RFSHCTL3(0)); 180 val = val ^ 0x2; 181 mmio_write_32(DDRC_RFSHCTL3(0), val); 182 183 /* Q4: only for legacy PHY, so here can skipped */ 184 185 /* dfi_frequency -> 0x1x */ 186 val = mmio_read_32(DDRC_DFIMISC(0)); 187 val &= 0xFE; 188 val |= (fsp_index << 8); 189 mmio_write_32(DDRC_DFIMISC(0), val); 190 /* dfi_init_start */ 191 val |= 0x20; 192 mmio_write_32(DDRC_DFIMISC(0), val); 193 194 /* polling dfi_init_complete de-assert */ 195 do { 196 val = mmio_read_32(DDRC_DFISTAT(0)); 197 } while ((val & 0x1) == 0x1); 198 199 /* change the clock frequency */ 200 dram_clock_switch(info->timing_info->fsp_table[fsp_index], info->bypass_mode); 201 202 /* dfi_init_start de-assert */ 203 mmio_clrbits_32(DDRC_DFIMISC(0), 0x20); 204 205 /* polling dfi_init_complete re-assert */ 206 do { 207 val = mmio_read_32(DDRC_DFISTAT(0)); 208 } while ((val & 0x1) == 0x0); 209 210 /* 27. set ZQCTL0.dis_srx_zqcl = 1 */ 211 if (fsp_index == 0) { 212 mmio_setbits_32(DDRC_ZQCTL0(0), BIT(30)); 213 } else if (fsp_index == 1) { 214 mmio_setbits_32(DDRC_FREQ1_ZQCTL0(0), BIT(30)); 215 } else { 216 mmio_setbits_32(DDRC_FREQ2_ZQCTL0(0), BIT(30)); 217 } 218 219 /* 28,29. exit "self refresh power down" to stay "self refresh 2" */ 220 /* exit SR power down */ 221 mmio_clrsetbits_32(DDRC_PWRCTL(0), 0x60, 0x40); 222 /* 30. Poll STAT.selfref_state in "Self refresh 2" */ 223 do { 224 val = mmio_read_32(DDRC_STAT(0)); 225 } while ((val & 0x300) != 0x300); 226 227 /* 31. change MR13.VRCG to normal */ 228 emr3 = (emr3 & 0x00f7) | 0x0d00; 229 lpddr4_mr_write(3, 13, emr3); 230 231 /* restore the PHY master */ 232 mmio_write_32(DDRC_DFIPHYMSTR(0), phy_master); 233 234 /* 32. issue ZQ if required: zq_calib_short, bit 4 */ 235 /* polling zq_calib_short_busy */ 236 mmio_setbits_32(DDRC_DBGCMD(0), 0x10); 237 238 do { 239 val = mmio_read_32(DDRC_DBGSTAT(0)); 240 } while ((val & 0x10) != 0x0); 241 242 /* 33. Reset ZQCTL0.dis_srx_zqcl=0 */ 243 if (fsp_index == 1) 244 mmio_clrbits_32(DDRC_FREQ1_ZQCTL0(0), BIT(30)); 245 else if (fsp_index == 2) 246 mmio_clrbits_32(DDRC_FREQ2_ZQCTL0(0), BIT(30)); 247 else 248 mmio_clrbits_32(DDRC_ZQCTL0(0), BIT(30)); 249 250 /* set SWCTL.dw_done to 1 and poll SWSTAT.sw_done_ack=1 */ 251 mmio_write_32(DDRC_SWCTL(0), 0x1); 252 253 /* wait SWSTAT.sw_done_ack to 1 */ 254 do { 255 val = mmio_read_32(DDRC_SWSTAT(0)); 256 } while ((val & 0x1) == 0x0); 257 258 /* 34. set PWRCTL.stay_in_selfreh=0, exit SR */ 259 mmio_clrbits_32(DDRC_PWRCTL(0), 0x40); 260 /* wait tXSR */ 261 262 /* 35. Poll STAT.selfref_state in "Idle" */ 263 do { 264 val = mmio_read_32(DDRC_STAT(0)); 265 } while ((val & 0x300) != 0x0); 266 267 #ifdef DFILP_SPT 268 /* 36. restore dfi_lp.dfi_lp_en_sr */ 269 mmio_setbits_32(DDRC_DFILPCFG0(0), BIT(8)); 270 #endif 271 272 /* 37. re-enable CAM: dis_dq */ 273 mmio_clrbits_32(DDRC_DBG1(0), 0x1); 274 275 /* 38. re-enable automatic SR: selfref_en */ 276 mmio_setbits_32(DDRC_PWRCTL(0), 0x1); 277 278 /* 39. re-enable automatic ZQ: dis_auto_zq=0 */ 279 /* disable automatic ZQ calibration */ 280 if (fsp_index == 1) 281 mmio_clrbits_32(DDRC_FREQ1_ZQCTL0(0), BIT(31)); 282 else if (fsp_index == 2) 283 mmio_clrbits_32(DDRC_FREQ2_ZQCTL0(0), BIT(31)); 284 else 285 mmio_clrbits_32(DDRC_ZQCTL0(0), BIT(31)); 286 /* 40. re-emable automatic derating: derate_enable */ 287 mmio_write_32(DDRC_DERATEEN(0), derate_backup[0]); 288 mmio_write_32(DDRC_FREQ1_DERATEEN(0), derate_backup[1]); 289 mmio_write_32(DDRC_FREQ2_DERATEEN(0), derate_backup[2]); 290 291 /* 41. write 1 to PCTRL.port_en */ 292 mmio_write_32(DDRC_PCTRL_0(0), 0x1); 293 294 /* 42. enable SBRCTL.scrub_en, skip if never enable it */ 295 } 296