Merge "feat(xilinx): deprecate PM_REQ_SUSPEND EEMI API" into integration

fix(rcar3): add missing image_base/size assignment to BL33 image loading path

Align BL33 image loading behavior in BL2 with BL3x image
loading behavior. BL31/BL32 image load already assigns
bl_mem_p

fix(rcar3): add missing image_base/size assignment to BL33 image loading path

Align BL33 image loading behavior in BL2 with BL3x image
loading behavior. BL31/BL32 image load already assigns
bl_mem_params->image_info.image_base and
bl_mem_params->image_info.image_size, but this assignment
is missing for BL33 image load.

This assignment is essential after retrieving the destination
address and size via rcar_get_dest_addr_from_cert(), so that
the parameters are passed correctly to the next stage. Without
this assignment, the BL33 image might not be loaded or validated
properly.

This change is not considered a vulnerability fix, but rather
a correction to ensure consistency and completeness in the BL2
image load logic.

Fixes: 4f7e0fa38fdb ("fix(rcar3): fix load address range check")
Signed-off-by: Hieu Nguyen <hieu.nguyen.dn@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> # Commit message update
Change-Id: I3c7c70f7f8d64b53e8c0f5ed61c71031b99fcde0

show more ...

feat(dsu): enable PMU registers access at EL1

- Disable trapping of write accesses to DSU cluster PMU registers
at EL3 and EL2.
- Clear the SPME bit in CLUSTERPMMDCR_EL3 to prohibit PMU event
co

feat(dsu): enable PMU registers access at EL1

- Disable trapping of write accesses to DSU cluster PMU registers
at EL3 and EL2.
- Clear the SPME bit in CLUSTERPMMDCR_EL3 to prohibit PMU event
counting in the secure state.

Change-Id: If3eb6e997330ae86f45760e0e862c003861f3d66
Signed-off-by: Amr Mohamed <amr.mohamed@arm.com>

show more ...

feat(rdaspen): add DSU to the device tree

Update the device tree file to include the AP's DSU clusters'
L3 cache and PMU info.

Change-Id: I0923b1aed1c92f8460370de197a6197de183d7f5
Signed-off-by: Am

feat(rdaspen): add DSU to the device tree

Update the device tree file to include the AP's DSU clusters'
L3 cache and PMU info.

Change-Id: I0923b1aed1c92f8460370de197a6197de183d7f5
Signed-off-by: Amr Mohamed <amr.mohamed@arm.com>
Signed-off-by: Ahmed Azeem <ahmed.azeem@arm.com>

show more ...

feat(rdaspen): add DSU support

- Enable use of the DSU driver through the `USE_DSU_DRIVER` flag.
This configures DSU power-down and power settings, using the
default reset values defined in the

feat(rdaspen): add DSU support

- Enable use of the DSU driver through the `USE_DSU_DRIVER` flag.
This configures DSU power-down and power settings, using the
default reset values defined in the DSU-120AE TRM.
- Enable the `PRESERVE_DSU_PMU_REGS` flag to save and restore DSU
cluster PMU registers across cluster power cycles.

Change-Id: I7f820981cd164a689324a525b506c2979bddb572
Signed-off-by: Amr Mohamed <amr.mohamed@arm.com>
Signed-off-by: Meet Patel <meet.patel2@arm.com>
Signed-off-by: Ahmed Azeem <ahmed.azeem@arm.com>

show more ...

docs(rdaspen): introduce rdaspen docs

RD-Aspen platform is formally introduced into the
documentation.

Refactors RD platforms separately, and a generic
Automotive RD index doc file is created.

Mai

docs(rdaspen): introduce rdaspen docs

RD-Aspen platform is formally introduced into the
documentation.

Refactors RD platforms separately, and a generic
Automotive RD index doc file is created.

Maintainers list updated for platform maintainer
of rdaspen.

Change-Id: I289a8caaa6f0e34e953f4101ee2814f1500bc9c8
Signed-off-by: Ahmed Azeem <ahmed.azeem@arm.com>

show more ...

feat(rdaspen): enable tbb on rd-aspen platform

Enable Trusted board boot on RD-Aspen platform.

Included the non-volatile(NV) memory region, to
ensure rollback protection.

Added Mbed TLS library in

feat(rdaspen): enable tbb on rd-aspen platform

Enable Trusted board boot on RD-Aspen platform.

Included the non-volatile(NV) memory region, to
ensure rollback protection.

Added Mbed TLS library initialization for MbedTLS
library.

Change-Id: I7940952c152b0243a91b38804cf16d3050ec2d4b
Signed-off-by: Sanjana Virupakshagouda <sanjana.virupakshagouda@arm.com>
Signed-off-by: Ahmed Azeem <ahmed.azeem@arm.com>

show more ...

feat(gicv3): add GIC-720AE model id

Add GIC-720AE model id to power up its Redistributor in BL31 GIC
initialization.
No use case so far for multichip support on GIC-720AE.

Change-Id: Id6ca8144b0c02

feat(gicv3): add GIC-720AE model id

Add GIC-720AE model id to power up its Redistributor in BL31 GIC
initialization.
No use case so far for multichip support on GIC-720AE.

Change-Id: Id6ca8144b0c02557ba7569a536cece37e4c1fe98
Signed-off-by: David Hu <david.hu2@arm.com>
Signed-off-by: Ahmed Azeem <ahmed.azeem@arm.com>

show more ...

feat(rdaspen): add BL31 for RD-Aspen platform

Implement BL31 for RD-Aspen platform.

* Implement power control features to incorporates an SCP via SCMI.
* Add the memory descriptor provides BL ima

feat(rdaspen): add BL31 for RD-Aspen platform

Implement BL31 for RD-Aspen platform.

* Implement power control features to incorporates an SCP via SCMI.
* Add the memory descriptor provides BL image information that gets
used by BL2 to load the images

Change-Id: I5f389c4a6ef9bc106b3b29c9aecbd890d91d99b3
Signed-off-by: Ahmed Azeem <ahmed.azeem@arm.com>
Signed-off-by: David Hu <david.hu2@arm.com>
Signed-off-by: Meet Patel <meet.patel2@arm.com>

show more ...

feat(rdaspen): introduce Arm RD-Aspen platform

Create a new platform for the RD-Aspen automotive FVP.
Add the required source, header files and makefile,and
device tree

This platform contains:
* C

feat(rdaspen): introduce Arm RD-Aspen platform

Create a new platform for the RD-Aspen automotive FVP.
Add the required source, header files and makefile,and
device tree

This platform contains:
* Cortex-A720AE, Armv9.2-A application processor
* A GICv4-compatible GIC-720AE
* 128 MB of SRAM, of which 512 KB is reserved for TF-A
* 4GiB of DRAM in two partitions (extensible)

It also adds:
* FW_CONFIG and HW_CONFIG device trees

Change-Id: I4ba3e4bf1fed8f3640f7eda815607b0a5cab9500
Signed-off-by: Ahmed Azeem <ahmed.azeem@arm.com>
Signed-off-by: David Hu <david.hu2@arm.com>
Signed-off-by: Meet Patel <meet.patel2@arm.com>

show more ...

build(dev-deps): bump the dev-deps group across 1 directory with 2 updates

Bumps the dev-deps group with 2 updates in the /tools/memory directory: [ruff](https://github.com/astral-sh/ruff) and [pyri

build(dev-deps): bump the dev-deps group across 1 directory with 2 updates

Bumps the dev-deps group with 2 updates in the /tools/memory directory: [ruff](https://github.com/astral-sh/ruff) and [pyright](https://github.com/RobertCraigie/pyright-python).


Updates `ruff` from 0.11.2 to 0.11.13
- [Release notes](https://github.com/astral-sh/ruff/releases)
- [Changelog](https://github.com/astral-sh/ruff/blob/0.11.13/CHANGELOG.md)
- [Commits](https://github.com/astral-sh/ruff/compare/0.11.2...0.11.13)

Updates `pyright` from 1.1.399 to 1.1.405
- [Release notes](https://github.com/RobertCraigie/pyright-python/releases)
- [Commits](https://github.com/RobertCraigie/pyright-python/compare/v1.1.399...v1.1.405)

--
updated-dependencies:
- dependency-name: ruff
dependency-version: 0.11.13
dependency-type: direct:development
update-type: version-update:semver-patch
dependency-group: dev-deps
- dependency-name: pyright
dependency-version: 1.1.405
dependency-type: direct:development
update-type: version-update:semver-patch
dependency-group: dev-deps
...

Change-Id: I30c5b4b7d614adff9ef58a0f1dcecae8fc8f083d
Signed-off-by: dependabot[bot] <support@github.com>

show more ...

Merge changes from topic "xl/corrupted-gpt" into integration

* changes:
feat(arm): implement arm platform GPT logging
feat(docs): platform hook to log GPT corruption
feat(guid-partition): plat

Merge changes from topic "xl/corrupted-gpt" into integration

* changes:
feat(arm): implement arm platform GPT logging
feat(docs): platform hook to log GPT corruption
feat(guid-partition): platform hook to log corrupted GPT

show more ...

feat(arm): implement arm platform GPT logging

The arm platform specific implementation of
logging corrupted primary GPT.

Change-Id: I73127668bcbf80e8fd2556da582fdcfc9ff9d524
Signed-off-by: Xialin L

feat(arm): implement arm platform GPT logging

The arm platform specific implementation of
logging corrupted primary GPT.

Change-Id: I73127668bcbf80e8fd2556da582fdcfc9ff9d524
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

show more ...

feat(docs): platform hook to log GPT corruption

The log GPT corruption add several platform hook for log GPT
corruption. Update the documentation for the functions.

Change-Id: Ia2ec3654c869801aece9

feat(docs): platform hook to log GPT corruption

The log GPT corruption add several platform hook for log GPT
corruption. Update the documentation for the functions.

Change-Id: Ia2ec3654c869801aece95b19ae5a5020cb01f905
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

show more ...

feat(guid-partition): platform hook to log corrupted GPT

Notification of the GPT corruption can be beneficial,
using the handoff structure from BL2 to
BL32 for logging the GPT corruption information

feat(guid-partition): platform hook to log corrupted GPT

Notification of the GPT corruption can be beneficial,
using the handoff structure from BL2 to
BL32 for logging the GPT corruption information

Change-Id: Ie1af7eb6d97ec76f3f6d1cffad292782bdedda21
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

show more ...

Merge "feat(mbedtls): update mbedtls to version 3.6.4" into integration

Merge "refactor(el3-runtime): move context security states to context.h" into integration

feat(fvp): add stub implementation for plat_lfa_notify_activate()

Introduce a stub for plat_lfa_notify_activate() in the FVP platform
code. This provides a placeholder implementation that always ret

feat(fvp): add stub implementation for plat_lfa_notify_activate()

Introduce a stub for plat_lfa_notify_activate() in the FVP platform
code. This provides a placeholder implementation that always returns
success as currently no notification is required.

Change-Id: I0e0813327af4f55e0aef12bd80a472d103ea317d
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

show more ...

feat(lfa): add platform hook for activation notification

Introduce a new platform API, plat_lfa_notify_activate(), which allows
the platform to notify its security engine to begin component
activati

feat(lfa): add platform hook for activation notification

Introduce a new platform API, plat_lfa_notify_activate(), which allows
the platform to notify its security engine to begin component
activation. The function accepts a component identifier and should
return 0 on success or an error code on failure.

Documentation and header files are updated accordingly, and the call is
integrated into the LFA activation path.

Change-Id: Ic66aa675bba62633cc92992b965d144a6f9ef129
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

show more ...

feat(mbedtls): update mbedtls to version 3.6.4

In order to successfully update mbedtls to version 3.6.4, the
redundant-decls warning must be disabled to accomodate a change in the
definition locatio

feat(mbedtls): update mbedtls to version 3.6.4

In order to successfully update mbedtls to version 3.6.4, the
redundant-decls warning must be disabled to accomodate a change in the
definition locations of some helper functions. This is currently an open
issue for mbedtls: https://github.com/Mbed-TLS/mbedtls/issues/10376

Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: I57c9c14aabe75a51c74dcf2a33faf59f95ce2386

show more ...

fix(intel): configure SCR1 for 32/16 non-secure SMRs and context banks

Update SCR1 register (0xFA000004) programming to:
- Set NSNUMSMRGO[14:8] = 0x20 to allocate 32 Stream Mapping Register
groups

fix(intel): configure SCR1 for 32/16 non-secure SMRs and context banks

Update SCR1 register (0xFA000004) programming to:
- Set NSNUMSMRGO[14:8] = 0x20 to allocate 32 Stream Mapping Register
groups for non-secure context.
- Set NSNUMCBO[5:0] = 0x10 to allocate 16 Context Banks for non-secure
context.

This change aligns with the requirement for SDM SMMU AFRL in Linux to
use 32 Context Banks. Secure and non-secure resources are now balanced,
with indices 0–31 reserved for non-secure and the rest for secure.

Change-Id: I6466a36278040d95b877f66a3800f13339d13bc8
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

show more ...

fix(intel): update the AES GCM/GCM_GHASH modes return data size

On the Agilex5 platform, in FCS AES method if block mode is
GCM/GCM_GHASH mode then the data size written to the destination
buffer is

fix(intel): update the AES GCM/GCM_GHASH modes return data size

On the Agilex5 platform, in FCS AES method if block mode is
GCM/GCM_GHASH mode then the data size written to the destination
buffer is at index[7] instead of [3] as in other cases.

Change-Id: Ide664f594ea63aaee7f74d21e8e2986de48e94a2
Signed-off-by: Girisha Dengi <girisha.dengi@altera.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

show more ...

fix(intel): undo setting USB 3.1 reset pulse bit in BL2

During testing of USB 3.1 in FreeRTOS, it is reported, setting
the reset pulse override bit is affecting the enumeration of
USB devices attach

fix(intel): undo setting USB 3.1 reset pulse bit in BL2

During testing of USB 3.1 in FreeRTOS, it is reported, setting
the reset pulse override bit is affecting the enumeration of
USB devices attached to the USB 3.1 controller. Hence,
reverting the bit change to its default state.

Change-Id: I5746a7ff6b579c39416a462ebef6696f4aa57051
Signed-off-by: Naresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

show more ...

refactor(fvp): always build RAS files

Their processing introduces a circular dependency with the
initialization of ENABLE_FEAT_RAS when it's not set on the commandline.
However, building them when E

refactor(fvp): always build RAS files

Their processing introduces a circular dependency with the
initialization of ENABLE_FEAT_RAS when it's not set on the commandline.
However, building them when ENABLE_FEAT_RAS=0 will not produce any side
effects and the code will never be called. So we can always build the
files to remove the circular check.

Change-Id: I44f90daa193c9b2c853f3fd9b54b67ccc7bace83
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

show more ...

fix(fvp): give fvp_ras.c better dependencies

PLATFORM_TEST_RAS_FFH should default to 0 when unset. It will always be
defined on the commandline so it needs to be checked for truthfulness.
SDEI_SUPPO

fix(fvp): give fvp_ras.c better dependencies

PLATFORM_TEST_RAS_FFH should default to 0 when unset. It will always be
defined on the commandline so it needs to be checked for truthfulness.
SDEI_SUPPORT will also be used so it must be set.

Change-Id: I0fed6ef40eee82a3624de7bc0c85f5662af4ca3a
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

show more ...