feat(imx93): add the basic support

Add the basic boot support for i.MX93.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I48bac2fd8bf2145133edf101a315908266c3f50a

feat(imx93): add the trdc driver

Add the trdc driver that is used on NXP i.MX9 family

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: Ie1fd86b76564fa7e20d74d5b4dbfe7ea0ee851fc

build(changelog): add new scopes for nxp imx platform

Add new scopes for NXP i.MX9 SoC family.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I65baaf5afbb174eecc22363ebc0396b6fadcd470

Merge changes from topic "gr/cpu_rename" into integration

* changes:
chore: rename hayes to a520
chore: rename hunter to a720
chore: rename hunter_elp to cortex-x4

chore: rename hayes to a520

Rename Cortex-hayes to Cortes-A520

Change-Id: Ic574b55b1aaf11b5bf7b583e244245e7b54bdb22
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

chore: rename hunter to a720

Rename cortex_hunter to cortex_a720

Change-Id: Id4e0e2cd47051c2e92b3f16373ea06ef4df1d75f
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

Merge "fix(fvp): adjust BL31 maximum size as per total SRAM size" into integration

chore: rename hunter_elp to cortex-x4

Rename hunter_elp to cortex-x4

Change-Id: I78c8c009d7bee14b4793dc1d950ed81273216831
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

Merge changes from topic "bk/context_refactor" into integration

* changes:
refactor(pmu): convert FEAT_MTPMU to C and move to persistent register init
feat(pmu): introduce pmuv3 lib/extensions f

Merge changes from topic "bk/context_refactor" into integration

* changes:
refactor(pmu): convert FEAT_MTPMU to C and move to persistent register init
feat(pmu): introduce pmuv3 lib/extensions folder
fix(pmu): make MDCR_EL3.MTPME=1 out of reset
refactor(cm): introduce a real manage_extensions_nonsecure()

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refactor(pmu): convert FEAT_MTPMU to C and move to persistent register init

The FEAT_MTPMU feature disable runs very early after reset. This means,
it needs to be written in assembly, since the C ru

refactor(pmu): convert FEAT_MTPMU to C and move to persistent register init

The FEAT_MTPMU feature disable runs very early after reset. This means,
it needs to be written in assembly, since the C runtime has not been
initialised yet.

However, there is no need for it to be initialised so soon. The PMU
state is only relevant after TF-A has relinquished control. The code
to do this is also very verbose and difficult to read. Delaying the
initialisation allows for it to happen with the rest of the PMU. Align
with FEAT_STATE in the process.

BREAKING CHANGE: This patch explicitly breaks the EL2 entry path. It is
currently unsupported.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I2aa659d026fbdb75152469f6d19812ece3488c6f

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feat(pmu): introduce pmuv3 lib/extensions folder

The enablement code for the PMU is scattered and difficult to track
down. Factor out the feature into its own lib/extensions folder and
consolidate t

feat(pmu): introduce pmuv3 lib/extensions folder

The enablement code for the PMU is scattered and difficult to track
down. Factor out the feature into its own lib/extensions folder and
consolidate the implementation. Treat it is as an architecturally
mandatory feature as it is currently.

Additionally, do some cleanup on AArch64. Setting overflow bits in
PMCR_EL0 is irrelevant for firmware so don't do it. Then delay the PMU
initialisation until the context management stage which simplifies the
early environment assembly. One side effect is that the PMU might count
before this happens so reset all counters to 0 to prevent any leakage.

Finally, add an enable to manage_extensions_realm() as realm world uses
the pmu. This introduces the HPMN fixup to realm world.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Ie13a8625820ecc5fbfa467dc6ca18025bf6a9cd3

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fix(pmu): make MDCR_EL3.MTPME=1 out of reset

Make the default value for MTPME always be 1 to preserve the reset
behaviour on newer revisions and on older revisions where the bit is
RES0 it doesn't m

fix(pmu): make MDCR_EL3.MTPME=1 out of reset

Make the default value for MTPME always be 1 to preserve the reset
behaviour on newer revisions and on older revisions where the bit is
RES0 it doesn't matter.

Before its introduction MDCR_EL3.MTPME was RES0. Upon its introduction
the field resets to 1, making the MTPMU architecturally "enabled". As
such, the logical action on TF-A's part is to "disable" it, which led to
the introduction of DISABLE_MTPMU.

This hinges on the assumption that MDCR_EL3.MTPME will always be 1
unless the above flag is set. Unfortunately this is not the case, as the
reset value is overwritten at reset with a macro that sets this bit to
0.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Ie570774972f246b3aa41dc016ecbcc6fc2f581f6

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refactor(cm): introduce a real manage_extensions_nonsecure()

manage_extensions_nonsecure() is problematic because it updates both
context and in-place registers (unlike its secure/realm counterparts

refactor(cm): introduce a real manage_extensions_nonsecure()

manage_extensions_nonsecure() is problematic because it updates both
context and in-place registers (unlike its secure/realm counterparts).
The in-place register updates make it particularly tricky, as those
never change for the lifetime of TF-A. However, they are only set when
exiting to NS world. As such, all of TF-A's execution before that
operates under a different context. This is inconsistent and could cause
problems.

This patch Introduce a real manage_extensions_nonsecure() which only
operates on the context structure. It also introduces a
cm_manage_extensions_el3() which only operates on register in-place that
are not context switched. It is called in BL31's entrypoints so that all
of TF-A executes with the same environment once all features have been
converted.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Ic579f86c41026d2054863ef44893e0ba4c591da9

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fix(fvp): adjust BL31 maximum size as per total SRAM size

Adjusted BL31 maximum size as per total SRAM size.

Change-Id: Ifdfdedb8af3e001cebba8e60c973f3c72be11652
Signed-off-by: Manish V Badarkhe <M

fix(fvp): adjust BL31 maximum size as per total SRAM size

Adjusted BL31 maximum size as per total SRAM size.

Change-Id: Ifdfdedb8af3e001cebba8e60c973f3c72be11652
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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fix(st-uart): correctly check UART enabled in flush fonction

Use tst instead of ands to check USART_CR1_UE bit is set. If not exit
the flush function.

Signed-off-by: Yann Gautier <yann.gautier@st.c

fix(st-uart): correctly check UART enabled in flush fonction

Use tst instead of ands to check USART_CR1_UE bit is set. If not exit
the flush function.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: Ibd2e18f6d8837073d0bbcb150e993985d3c0dd6f

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Merge changes from topic "ms/cpu_errata" into integration

* changes:
refactor(cpus): add Cortex-A72 errata information
refactor(cpus): convert Rainier to use errata framework
refactor(cpus): c

Merge changes from topic "ms/cpu_errata" into integration

* changes:
refactor(cpus): add Cortex-A72 errata information
refactor(cpus): convert Rainier to use errata framework
refactor(cpus): convert QEMU Max to use the errata framework

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Merge "docs: remove deprecated tc0 from list of supported FVPs" into integration

Merge "feat(qemu_sbsa): handle GIC ITS address" into integration

feat(qemu_sbsa): handle GIC ITS address

Read data from DeviceTree provided by QEMU, provide via SMC
to the next firmware level.

Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Cha

feat(qemu_sbsa): handle GIC ITS address

Read data from DeviceTree provided by QEMU, provide via SMC
to the next firmware level.

Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Change-Id: I95c5f00ab2cca3b5fda122dcc8d7704a7a82059b

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refactor(cpus): convert the Cortex-A75 to use cpu helpers

Testing done in conjunction with change 258152.

Signed-off-by: Kathleen Capella <kathleen.capella@arm.com>
Change-Id: I9082c7a5c68e39d6e419

refactor(cpus): convert the Cortex-A75 to use cpu helpers

Testing done in conjunction with change 258152.

Signed-off-by: Kathleen Capella <kathleen.capella@arm.com>
Change-Id: I9082c7a5c68e39d6e419c2a00501d63895ca73c7

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refactor(cpus): convert the Cortex-A75 to use the errata framework

This involves replacing:
* the reset_func with the standard cpu_reset_func_{start,end} to apply
errata automatically
* the <cp

refactor(cpus): convert the Cortex-A75 to use the errata framework

This involves replacing:
* the reset_func with the standard cpu_reset_func_{start,end} to apply
errata automatically
* the <cpu>_errata_report with the errata_report_shim to report errata
automatically
...and for each erratum:
* the prologue with the workaround_<type>_start to do the checks and
framework registration automatically
* the epilogue with the workaround_<type>_end
* the checker function with the check_erratum_<type> to make it more
descriptive

It is important to note that the errata workaround sequences remain
unchanged and preserve their git blame.

Testing was conducted by:
* Building for release with all errata flags enabled and running script
in change 19136 to compare output of objdump for each errata. Only
ERRATA_A75_764081 and ERRATA_A75_790748 could be verified this way,
rest had to be manually verified.
* Manual comparison of disassembly of converted functions with non-
converted functions

aarch64-none-elf-objdump -D <trusted-firmware-a with conversion>/build/fvp/release/bl31/bl31.elf
vs
aarch64-none-elf-objdump -D <trusted-firmware-a clean repo>/build/fvp/release/bl31/bl31.elf

* Build for release with all errata flags enabled and run default tftf
tests

CROSS_COMPILE=aarch64-none-elf- make PLAT=fvp HW_ASSISTED_COHERENCY=1 \
USE_COHERENT_MEM=0 CTX_INCLUDE_AARCH32_REGS=1 \
BL33=/home/katcap01/tf-a-tests/build/fvp/debug/tftf.bin \
ERRATA_A75_764081=1 ERRATA_A75_790748=1 WORKAROUND_CVE_2017_5715=1 \
WORKAROUND_CVE_2018_3639=1 \
ERRATA_DSU_798953=1 ERRATA_DSU_936184=1 \
WORKAROUND_CVE_2022_23960=1 \
fip all

* Build for debug with all errata enabled and step through ArmDS
at reset to ensure all functions are entered.
Signed-off-by: Kathleen Capella <kathleen.capella@arm.com>
Change-Id: I0cd393db825fcb5c7ddea3aa2a5934ffc4b6046e

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Merge "feat(cpus): add support for hermes cpu" into integration

feat(mt8195): increase TZRAM

We need 4k more memory.

Change-Id: I760e949c2f80a79e111060b24855c0a6a5bfdfaa
Signed-off-by: Yi Chou <yich@google.com>

feat(cpus): add support for hermes cpu

Adding basic CPU library code to support the Hermes CPU.

Change-Id: I61946033fe5fafb56ceb2d14d4c796d85b30457e
Signed-off-by: Govindraj Raja <govindraj.raja@ar

feat(cpus): add support for hermes cpu

Adding basic CPU library code to support the Hermes CPU.

Change-Id: I61946033fe5fafb56ceb2d14d4c796d85b30457e
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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refactor(cpus): add Cortex-A72 errata information

* adds add_erratum_etnry for all described erratas.
* replaces errata_report function with errata_report_shim to report
errata automatically

Change

refactor(cpus): add Cortex-A72 errata information

* adds add_erratum_etnry for all described erratas.
* replaces errata_report function with errata_report_shim to report
errata automatically

Change-Id: I7e3315d5cc77b77c328fff7f3988ec588b8f88b9
Signed-off-by: Maksims Svecovs <maksims.svecovs@arm.com>

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