1/* 2 * Copyright (c) 2021-2023, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a710.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Cortex A710 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Cortex A710 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25#if WORKAROUND_CVE_2022_23960 26 wa_cve_2022_23960_bhb_vector_table CORTEX_A710_BHB_LOOP_COUNT, cortex_a710 27#endif /* WORKAROUND_CVE_2022_23960 */ 28 29/* -------------------------------------------------- 30 * Errata Workaround for Cortex-A710 Erratum 1987031. 31 * This applies to revision r0p0, r1p0 and r2p0 of Cortex-A710. It is still 32 * open. 33 * Inputs: 34 * x0: variant[4:7] and revision[0:3] of current cpu. 35 * Shall clobber: x0-x17 36 * -------------------------------------------------- 37 */ 38func errata_a710_1987031_wa 39 /* Check revision. */ 40 mov x17, x30 41 bl check_errata_1987031 42 cbz x0, 1f 43 44 /* Apply instruction patching sequence */ 45 ldr x0,=0x6 46 msr S3_6_c15_c8_0,x0 47 ldr x0,=0xF3A08002 48 msr S3_6_c15_c8_2,x0 49 ldr x0,=0xFFF0F7FE 50 msr S3_6_c15_c8_3,x0 51 ldr x0,=0x40000001003ff 52 msr S3_6_c15_c8_1,x0 53 ldr x0,=0x7 54 msr S3_6_c15_c8_0,x0 55 ldr x0,=0xBF200000 56 msr S3_6_c15_c8_2,x0 57 ldr x0,=0xFFEF0000 58 msr S3_6_c15_c8_3,x0 59 ldr x0,=0x40000001003f3 60 msr S3_6_c15_c8_1,x0 61 isb 621: 63 ret x17 64endfunc errata_a710_1987031_wa 65 66func check_errata_1987031 67 /* Applies to r0p0, r1p0 and r2p0 */ 68 mov x1, #0x20 69 b cpu_rev_var_ls 70endfunc check_errata_1987031 71 72/* --------------------------------------------------------------- 73 * Errata Workaround for Cortex-A710 Erratum 2008768. 74 * This applies to revision r0p0, r1p0 and r2p0. 75 * It is fixed in r2p1. 76 * Inputs: 77 * x0: variant[4:7] and revision[0:3] of current cpu. 78 * Shall clobber: x0, x1, x2, x17 79 * --------------------------------------------------------------- 80 */ 81func errata_a710_2008768_wa 82 mov x17, x30 83 bl check_errata_2008768 84 cbz x0, 1f 85 86 /* Stash ERRSELR_EL1 in x2 */ 87 mrs x2, ERRSELR_EL1 88 89 /* Select error record 0 and clear ED bit */ 90 msr ERRSELR_EL1, xzr 91 mrs x1, ERXCTLR_EL1 92 bfi x1, xzr, #ERXCTLR_ED_SHIFT, #1 93 msr ERXCTLR_EL1, x1 94 95 /* Select error record 1 and clear ED bit */ 96 mov x0, #1 97 msr ERRSELR_EL1, x0 98 mrs x1, ERXCTLR_EL1 99 bfi x1, xzr, #ERXCTLR_ED_SHIFT, #1 100 msr ERXCTLR_EL1, x1 101 102 /* Restore ERRSELR_EL1 from x2 */ 103 msr ERRSELR_EL1, x2 104 1051: 106 ret x17 107endfunc errata_a710_2008768_wa 108 109func check_errata_2008768 110 /* Applies to r0p0, r1p0 and r2p0 */ 111 mov x1, #0x20 112 b cpu_rev_var_ls 113endfunc check_errata_2008768 114 115/* ------------------------------------------------------------- 116 * Errata Workaround for Cortex-A710 Erratum 2017096. 117 * This applies to revisions r0p0, r1p0 and r2p0 of Cortex-A710. 118 * Inputs: 119 * x0: variant[4:7] and revision[0:3] of current cpu. 120 * Shall clobber: x0-x17 121 * ------------------------------------------------------------- 122 */ 123func errata_a710_2017096_wa 124 /* Compare x0 against revision r0p0 to r2p0 */ 125 mov x17, x30 126 bl check_errata_2017096 127 cbz x0, 1f 128 mrs x1, CORTEX_A710_CPUECTLR_EL1 129 orr x1, x1, CORTEX_A710_CPUECTLR_EL1_PFSTIDIS_BIT 130 msr CORTEX_A710_CPUECTLR_EL1, x1 131 1321: 133 ret x17 134endfunc errata_a710_2017096_wa 135 136func check_errata_2017096 137 /* Applies to r0p0, r1p0, r2p0 */ 138 mov x1, #0x20 139 b cpu_rev_var_ls 140endfunc check_errata_2017096 141 142/* --------------------------------------------------------------------- 143 * Errata Workaround for Cortex-A710 Erratum 2055002. 144 * This applies to revision r1p0, r2p0 of Cortex-A710 and is still open. 145 * Inputs: 146 * x0: variant[4:7] and revision[0:3] of current cpu. 147 * Shall clobber: x0-x17 148 * --------------------------------------------------------------------- 149 */ 150func errata_a710_2055002_wa 151 /* Compare x0 against revision r2p0 */ 152 mov x17, x30 153 bl check_errata_2055002 154 cbz x0, 1f 155 mrs x1, CORTEX_A710_CPUACTLR_EL1 156 orr x1, x1, CORTEX_A710_CPUACTLR_EL1_BIT_46 157 msr CORTEX_A710_CPUACTLR_EL1, x1 1581: 159 ret x17 160endfunc errata_a710_2055002_wa 161 162func check_errata_2055002 163 /* Applies to r1p0, r2p0 */ 164 mov x1, #0x20 165 b cpu_rev_var_ls 166endfunc check_errata_2055002 167 168/* --------------------------------------------------------------------- 169 * Errata Workaround for Cortex-A710 Erratum 2058056. 170 * This applies to revisions r0p0, r1p0 and r2p0 of Cortex-A710 and is still 171 * open. 172 * Inputs: 173 * x0: variant[4:7] and revision[0:3] of current cpu. 174 * Shall clobber: x0-x17 175 * --------------------------------------------------------------------- 176 */ 177func errata_a710_2058056_wa 178 /* Compare x0 against revision r2p0 */ 179 mov x17, x30 180 bl check_errata_2058056 181 cbz x0, 1f 182 mrs x1, CORTEX_A710_CPUECTLR2_EL1 183 mov x0, #CORTEX_A710_CPUECTLR2_EL1_PF_MODE_CNSRV 184 bfi x1, x0, #CPUECTLR2_EL1_PF_MODE_LSB, #CPUECTLR2_EL1_PF_MODE_WIDTH 185 msr CORTEX_A710_CPUECTLR2_EL1, x1 1861: 187 ret x17 188endfunc errata_a710_2058056_wa 189 190func check_errata_2058056 191 /* Applies to r0p0, r1p0 and r2p0 */ 192 mov x1, #0x20 193 b cpu_rev_var_ls 194endfunc check_errata_2058056 195 196/* -------------------------------------------------- 197 * Errata Workaround for Cortex-A710 Erratum 2081180. 198 * This applies to revision r0p0, r1p0 and r2p0 of Cortex-A710. 199 * It is still open. 200 * Inputs: 201 * x0: variant[4:7] and revision[0:3] of current cpu. 202 * Shall clobber: x0-x17 203 * -------------------------------------------------- 204 */ 205func errata_a710_2081180_wa 206 /* Check revision. */ 207 mov x17, x30 208 bl check_errata_2081180 209 cbz x0, 1f 210 211 /* Apply instruction patching sequence */ 212 ldr x0,=0x3 213 msr S3_6_c15_c8_0,x0 214 ldr x0,=0xF3A08002 215 msr S3_6_c15_c8_2,x0 216 ldr x0,=0xFFF0F7FE 217 msr S3_6_c15_c8_3,x0 218 ldr x0,=0x10002001003FF 219 msr S3_6_c15_c8_1,x0 220 ldr x0,=0x4 221 msr S3_6_c15_c8_0,x0 222 ldr x0,=0xBF200000 223 msr S3_6_c15_c8_2,x0 224 ldr x0,=0xFFEF0000 225 msr S3_6_c15_c8_3,x0 226 ldr x0,=0x10002001003F3 227 msr S3_6_c15_c8_1,x0 228 isb 2291: 230 ret x17 231endfunc errata_a710_2081180_wa 232 233func check_errata_2081180 234 /* Applies to r0p0, r1p0 and r2p0 */ 235 mov x1, #0x20 236 b cpu_rev_var_ls 237endfunc check_errata_2081180 238 239 240/* --------------------------------------------------------------------- 241 * Errata Workaround for Cortex-A710 Erratum 2083908. 242 * This applies to revision r2p0 of Cortex-A710 and is still open. 243 * Inputs: 244 * x0: variant[4:7] and revision[0:3] of current cpu. 245 * Shall clobber: x0-x17 246 * --------------------------------------------------------------------- 247 */ 248func errata_a710_2083908_wa 249 /* Compare x0 against revision r2p0 */ 250 mov x17, x30 251 bl check_errata_2083908 252 cbz x0, 1f 253 mrs x1, CORTEX_A710_CPUACTLR5_EL1 254 orr x1, x1, CORTEX_A710_CPUACTLR5_EL1_BIT_13 255 msr CORTEX_A710_CPUACTLR5_EL1, x1 2561: 257 ret x17 258endfunc errata_a710_2083908_wa 259 260func check_errata_2083908 261 /* Applies to r2p0 */ 262 mov x1, #CPU_REV(2, 0) 263 mov x2, #CPU_REV(2, 0) 264 b cpu_rev_var_range 265endfunc check_errata_2083908 266 267/* --------------------------------------------------------------- 268 * Errata Workaround for Cortex-A710 Erratum 2136059. 269 * This applies to revision r0p0, r1p0 and r2p0. 270 * It is fixed in r2p1. 271 * Inputs: 272 * x0: variant[4:7] and revision[0:3] of current cpu. 273 * Shall clobber: x0-x17 274 * --------------------------------------------------------------- 275 */ 276func errata_a710_2136059_wa 277 /* Compare x0 against revision r2p0 */ 278 mov x17, x30 279 bl check_errata_2136059 280 cbz x0, 1f 281 282 /* Apply the workaround */ 283 mrs x1, CORTEX_A710_CPUACTLR5_EL1 284 orr x1, x1, CORTEX_A710_CPUACTLR5_EL1_BIT_44 285 msr CORTEX_A710_CPUACTLR5_EL1, x1 286 2871: 288 ret x17 289endfunc errata_a710_2136059_wa 290 291func check_errata_2136059 292 /* Applies to r0p0, r1p0 and r2p0 */ 293 mov x1, #0x20 294 b cpu_rev_var_ls 295endfunc check_errata_2136059 296 297/* ---------------------------------------------------------------- 298 * Errata workaround for Cortex-A710 Erratum 2147715. 299 * This applies to revision r2p0, and is fixed in r2p1. 300 * Inputs: 301 * x0: variant[4:7] and revision[0:3] of current cpu. 302 * Shall clobber: x0, x1, x17 303 * ---------------------------------------------------------------- 304 */ 305func errata_a710_2147715_wa 306 mov x17, x30 307 bl check_errata_2147715 308 cbz x0, 1f 309 310 /* Apply workaround; set CPUACTLR_EL1[22] 311 * to 1, which will cause the CFP instruction 312 * to invalidate all branch predictor resources 313 * regardless of context. 314 */ 315 mrs x1, CORTEX_A710_CPUACTLR_EL1 316 orr x1, x1, CORTEX_A710_CPUACTLR_EL1_BIT_22 317 msr CORTEX_A710_CPUACTLR_EL1, x1 3181: 319 ret x17 320endfunc errata_a710_2147715_wa 321 322func check_errata_2147715 323 mov x1, #0x20 324 mov x2, #0x20 325 b cpu_rev_var_range 326endfunc check_errata_2147715 327 328/* --------------------------------------------------------------- 329 * Errata Workaround for Cortex-A710 Erratum 2216384. 330 * This applies to revision r0p0, r1p0 and r2p0. 331 * It is fixed in r2p1. 332 * Inputs: 333 * x0: variant[4:7] and revision[0:3] of current cpu. 334 * Shall clobber: x0-x17 335 * --------------------------------------------------------------- 336 */ 337func errata_a710_2216384_wa 338 /* Compare x0 against revision r2p0 */ 339 mov x17, x30 340 bl check_errata_2216384 341 cbz x0, 1f 342 343 /* Apply workaround: set CPUACTLR5_EL1[17] 344 * to 1 and the following instruction 345 * patching sequence. 346 */ 347 mrs x1, CORTEX_A710_CPUACTLR5_EL1 348 orr x1, x1, CORTEX_A710_CPUACTLR5_EL1_BIT_17 349 msr CORTEX_A710_CPUACTLR5_EL1, x1 350 351 ldr x0,=0x5 352 msr CORTEX_A710_CPUPSELR_EL3, x0 353 ldr x0,=0x10F600E000 354 msr CORTEX_A710_CPUPOR_EL3, x0 355 ldr x0,=0x10FF80E000 356 msr CORTEX_A710_CPUPMR_EL3, x0 357 ldr x0,=0x80000000003FF 358 msr CORTEX_A710_CPUPCR_EL3, x0 359 isb 3601: 361 ret x17 362endfunc errata_a710_2216384_wa 363 364func check_errata_2216384 365 /* Applies to r0p0, r1p0 and r2p0 */ 366 mov x1, #0x20 367 b cpu_rev_var_ls 368endfunc check_errata_2216384 369 370/* -------------------------------------------------- 371 * Errata Workaround for Cortex-A710 Erratum 2267065. 372 * This applies to revisions r0p0, r1p0 and r2p0. 373 * It is fixed in r2p1. 374 * Inputs: 375 * x0: variant[4:7] and revision[0:3] of current cpu. 376 * Shall clobber: x0-x1, x17 377 * -------------------------------------------------- 378 */ 379func errata_a710_2267065_wa 380 /* Compare x0 against revision r2p0 */ 381 mov x17, x30 382 bl check_errata_2267065 383 cbz x0, 1f 384 385 /* Apply instruction patching sequence */ 386 mrs x1, CORTEX_A710_CPUACTLR_EL1 387 orr x1, x1, CORTEX_A710_CPUACTLR_EL1_BIT_22 388 msr CORTEX_A710_CPUACTLR_EL1, x1 3891: 390 ret x17 391endfunc errata_a710_2267065_wa 392 393func check_errata_2267065 394 /* Applies to r0p0, r1p0 and r2p0 */ 395 mov x1, #0x20 396 b cpu_rev_var_ls 397endfunc check_errata_2267065 398 399/* --------------------------------------------------------------- 400 * Errata Workaround for Cortex-A710 Erratum 2282622. 401 * This applies to revision r0p0, r1p0, r2p0 and r2p1. 402 * It is still open. 403 * Inputs: 404 * x0: variant[4:7] and revision[0:3] of current cpu. 405 * Shall clobber: x0, x1, x17 406 * --------------------------------------------------------------- 407 */ 408func errata_a710_2282622_wa 409 /* Compare x0 against revision r2p1 */ 410 mov x17, x30 411 bl check_errata_2282622 412 cbz x0, 1f 413 414 /* Apply the workaround */ 415 mrs x1, CORTEX_A710_CPUACTLR2_EL1 416 orr x1, x1, #BIT(0) 417 msr CORTEX_A710_CPUACTLR2_EL1, x1 418 4191: 420 ret x17 421endfunc errata_a710_2282622_wa 422 423func check_errata_2282622 424 /* Applies to r0p0, r1p0, r2p0 and r2p1 */ 425 mov x1, #0x21 426 b cpu_rev_var_ls 427endfunc check_errata_2282622 428 429/* ------------------------------------------------------------------------ 430 * Errata Workaround for Cortex-A710 Erratum 2291219 on power down request. 431 * This applies to revision <= r2p0 and is fixed in r2p1. 432 * Inputs: 433 * x0: variant[4:7] and revision[0:3] of current cpu. 434 * Shall clobber: x0-x1, x17 435 * ------------------------------------------------------------------------ 436 */ 437func errata_a710_2291219_wa 438 /* Check revision. */ 439 mov x17, x30 440 bl check_errata_2291219 441 cbz x0, 1f 442 443 /* Set bit 36 in ACTLR2_EL1 */ 444 mrs x1, CORTEX_A710_CPUACTLR2_EL1 445 orr x1, x1, #CORTEX_A710_CPUACTLR2_EL1_BIT_36 446 msr CORTEX_A710_CPUACTLR2_EL1, x1 4471: 448 ret x17 449endfunc errata_a710_2291219_wa 450 451func check_errata_2291219 452 /* Applies to <= r2p0. */ 453 mov x1, #0x20 454 b cpu_rev_var_ls 455endfunc check_errata_2291219 456 457/* ------------------------------------------------------- 458 * Errata Workaround for Cortex-A710 Erratum 2371105. 459 * This applies to revisions <= r2p0 and is fixed in r2p1. 460 * x0: variant[4:7] and revision[0:3] of current cpu. 461 * Shall clobber: x0-x17 462 * ------------------------------------------------------- 463 */ 464func errata_a710_2371105_wa 465 /* Check workaround compatibility. */ 466 mov x17, x30 467 bl check_errata_2371105 468 cbz x0, 1f 469 470 /* Set bit 40 in CPUACTLR2_EL1 */ 471 mrs x1, CORTEX_A710_CPUACTLR2_EL1 472 orr x1, x1, #CORTEX_A710_CPUACTLR2_EL1_BIT_40 473 msr CORTEX_A710_CPUACTLR2_EL1, x1 474 isb 4751: 476 ret x17 477endfunc errata_a710_2371105_wa 478 479func check_errata_2371105 480 /* Applies to <= r2p0. */ 481 mov x1, #0x20 482 b cpu_rev_var_ls 483endfunc check_errata_2371105 484 485/* ---------------------------------------------------- 486 * Errata Workaround for Cortex-A710 Errata #2768515 487 * This applies to revisions <= r2p1 and is still open. 488 * x0: variant[4:7] and revision[0:3] of current cpu. 489 * Shall clobber: x0-x17 490 * ---------------------------------------------------- 491 */ 492func errata_a710_2768515_wa 493 mov x17, x30 494 bl check_errata_2768515 495 cbz x0, 1f 496 497 /* dsb before isb of power down sequence */ 498 dsb sy 4991: 500 ret x17 501endfunc errata_a710_2768515_wa 502 503func check_errata_2768515 504 /* Applies to all revisions <= r2p1 */ 505 mov x1, #0x21 506 b cpu_rev_var_ls 507endfunc check_errata_2768515 508 509func check_errata_cve_2022_23960 510#if WORKAROUND_CVE_2022_23960 511 mov x0, #ERRATA_APPLIES 512#else 513 mov x0, #ERRATA_MISSING 514#endif 515 ret 516endfunc check_errata_cve_2022_23960 517 518 /* ---------------------------------------------------- 519 * HW will do the cache maintenance while powering down 520 * ---------------------------------------------------- 521 */ 522func cortex_a710_core_pwr_dwn 523 524#if ERRATA_A710_2008768 525 mov x4, x30 526 bl cpu_get_rev_var 527 bl errata_a710_2008768_wa 528 mov x30, x4 529#endif 530 531#if ERRATA_A710_2291219 532 mov x15, x30 533 bl cpu_get_rev_var 534 bl errata_a710_2291219_wa 535 mov x30, x15 536#endif /* ERRATA_A710_2291219 */ 537 538 /* --------------------------------------------------- 539 * Enable CPU power down bit in power control register 540 * --------------------------------------------------- 541 */ 542 mrs x0, CORTEX_A710_CPUPWRCTLR_EL1 543 orr x0, x0, #CORTEX_A710_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 544 msr CORTEX_A710_CPUPWRCTLR_EL1, x0 545#if ERRATA_A710_2768515 546 mov x15, x30 547 bl cpu_get_rev_var 548 bl errata_a710_2768515_wa 549 mov x30, x15 550#endif /* ERRATA_A710_2768515 */ 551 isb 552 ret 553endfunc cortex_a710_core_pwr_dwn 554 555#if REPORT_ERRATA 556 /* 557 * Errata printing function for Cortex-A710. Must follow AAPCS. 558 */ 559func cortex_a710_errata_report 560 stp x8, x30, [sp, #-16]! 561 562 bl cpu_get_rev_var 563 mov x8, x0 564 565 /* 566 * Report all errata. The revision-variant information is passed to 567 * checking functions of each errata. 568 */ 569 report_errata ERRATA_A710_1987031, cortex_a710, 1987031 570 report_errata ERRATA_A710_2081180, cortex_a710, 2081180 571 report_errata ERRATA_A710_2055002, cortex_a710, 2055002 572 report_errata ERRATA_A710_2017096, cortex_a710, 2017096 573 report_errata ERRATA_A710_2083908, cortex_a710, 2083908 574 report_errata ERRATA_A710_2058056, cortex_a710, 2058056 575 report_errata ERRATA_A710_2267065, cortex_a710, 2267065 576 report_errata ERRATA_A710_2136059, cortex_a710, 2136059 577 report_errata ERRATA_A710_2282622, cortex_a710, 2282622 578 report_errata ERRATA_A710_2008768, cortex_a710, 2008768 579 report_errata ERRATA_A710_2147715, cortex_a710, 2147715 580 report_errata ERRATA_A710_2216384, cortex_a710, 2216384 581 report_errata ERRATA_A710_2291219, cortex_a710, 2291219 582 report_errata ERRATA_A710_2371105, cortex_a710, 2371105 583 report_errata ERRATA_A710_2768515, cortex_a710, 2768515 584 report_errata WORKAROUND_CVE_2022_23960, cortex_a710, cve_2022_23960 585 report_errata ERRATA_DSU_2313941, cortex_a710, dsu_2313941 586 587 ldp x8, x30, [sp], #16 588 ret 589endfunc cortex_a710_errata_report 590#endif 591 592func cortex_a710_reset_func 593 mov x19, x30 594 595 /* Disable speculative loads */ 596 msr SSBS, xzr 597 598 bl cpu_get_rev_var 599 mov x18, x0 600 601#if ERRATA_DSU_2313941 602 bl errata_dsu_2313941_wa 603#endif 604 605#if ERRATA_A710_1987031 606 mov x0, x18 607 bl errata_a710_1987031_wa 608#endif 609 610#if ERRATA_A710_2081180 611 mov x0, x18 612 bl errata_a710_2081180_wa 613#endif 614 615#if ERRATA_A710_2055002 616 mov x0, x18 617 bl errata_a710_2055002_wa 618#endif 619 620#if ERRATA_A710_2017096 621 mov x0, x18 622 bl errata_a710_2017096_wa 623#endif 624 625#if ERRATA_A710_2083908 626 mov x0, x18 627 bl errata_a710_2083908_wa 628#endif 629 630#if ERRATA_A710_2058056 631 mov x0, x18 632 bl errata_a710_2058056_wa 633#endif 634 635#if ERRATA_A710_2267065 636 mov x0, x18 637 bl errata_a710_2267065_wa 638#endif 639 640#if ERRATA_A710_2136059 641 mov x0, x18 642 bl errata_a710_2136059_wa 643#endif 644 645#if ERRATA_A710_2147715 646 mov x0, x18 647 bl errata_a710_2147715_wa 648#endif 649 650#if ERRATA_A710_2216384 651 mov x0, x18 652 bl errata_a710_2216384_wa 653#endif /* ERRATA_A710_2216384 */ 654 655#if ERRATA_A710_2282622 656 mov x0, x18 657 bl errata_a710_2282622_wa 658#endif 659 660#if ERRATA_A710_2371105 661 mov x0, x18 662 bl errata_a710_2371105_wa 663#endif 664 665#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960 666 /* 667 * The Cortex-A710 generic vectors are overridden to apply errata 668 * mitigation on exception entry from lower ELs. 669 */ 670 adr x0, wa_cve_vbar_cortex_a710 671 msr vbar_el3, x0 672#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */ 673 674 isb 675 ret x19 676endfunc cortex_a710_reset_func 677 678 /* --------------------------------------------- 679 * This function provides Cortex-A710 specific 680 * register information for crash reporting. 681 * It needs to return with x6 pointing to 682 * a list of register names in ascii and 683 * x8 - x15 having values of registers to be 684 * reported. 685 * --------------------------------------------- 686 */ 687.section .rodata.cortex_a710_regs, "aS" 688cortex_a710_regs: /* The ascii list of register names to be reported */ 689 .asciz "cpuectlr_el1", "" 690 691func cortex_a710_cpu_reg_dump 692 adr x6, cortex_a710_regs 693 mrs x8, CORTEX_A710_CPUECTLR_EL1 694 ret 695endfunc cortex_a710_cpu_reg_dump 696 697declare_cpu_ops cortex_a710, CORTEX_A710_MIDR, \ 698 cortex_a710_reset_func, \ 699 cortex_a710_core_pwr_dwn 700