1/* 2 * Copyright (c) 2021-2023, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a710.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Cortex A710 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Cortex A710 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25#if WORKAROUND_CVE_2022_23960 26 wa_cve_2022_23960_bhb_vector_table CORTEX_A710_BHB_LOOP_COUNT, cortex_a710 27#endif /* WORKAROUND_CVE_2022_23960 */ 28 29workaround_reset_start cortex_a710, ERRATUM(1987031), ERRATA_A710_1987031 30 ldr x0,=0x6 31 msr S3_6_c15_c8_0,x0 32 ldr x0,=0xF3A08002 33 msr S3_6_c15_c8_2,x0 34 ldr x0,=0xFFF0F7FE 35 msr S3_6_c15_c8_3,x0 36 ldr x0,=0x40000001003ff 37 msr S3_6_c15_c8_1,x0 38 ldr x0,=0x7 39 msr S3_6_c15_c8_0,x0 40 ldr x0,=0xBF200000 41 msr S3_6_c15_c8_2,x0 42 ldr x0,=0xFFEF0000 43 msr S3_6_c15_c8_3,x0 44 ldr x0,=0x40000001003f3 45 msr S3_6_c15_c8_1,x0 46workaround_reset_end cortex_a710, ERRATUM(1987031) 47 48check_erratum_ls cortex_a710, ERRATUM(1987031), CPU_REV(2, 0) 49 50workaround_runtime_start cortex_a710, ERRATUM(2008768), ERRATA_A710_2008768 51 /* Stash ERRSELR_EL1 in x2 */ 52 mrs x2, ERRSELR_EL1 53 54 /* Select error record 0 and clear ED bit */ 55 msr ERRSELR_EL1, xzr 56 mrs x1, ERXCTLR_EL1 57 bfi x1, xzr, #ERXCTLR_ED_SHIFT, #1 58 msr ERXCTLR_EL1, x1 59 60 /* Select error record 1 and clear ED bit */ 61 mov x0, #1 62 msr ERRSELR_EL1, x0 63 mrs x1, ERXCTLR_EL1 64 bfi x1, xzr, #ERXCTLR_ED_SHIFT, #1 65 msr ERXCTLR_EL1, x1 66 67 /* Restore ERRSELR_EL1 from x2 */ 68 msr ERRSELR_EL1, x2 69workaround_runtime_end cortex_a710, ERRATUM(2008768), NO_ISB 70 71check_erratum_ls cortex_a710, ERRATUM(2008768), CPU_REV(2, 0) 72 73workaround_reset_start cortex_a710, ERRATUM(2017096), ERRATA_A710_2017096 74 mrs x1, CORTEX_A710_CPUECTLR_EL1 75 orr x1, x1, CORTEX_A710_CPUECTLR_EL1_PFSTIDIS_BIT 76 msr CORTEX_A710_CPUECTLR_EL1, x1 77workaround_reset_end cortex_a710, ERRATUM(2017096) 78 79check_erratum_ls cortex_a710, ERRATUM(2017096), CPU_REV(2, 0) 80 81workaround_reset_start cortex_a710, ERRATUM(2055002), ERRATA_A710_2055002 82 mrs x1, CORTEX_A710_CPUACTLR_EL1 83 orr x1, x1, CORTEX_A710_CPUACTLR_EL1_BIT_46 84 msr CORTEX_A710_CPUACTLR_EL1, x1 85workaround_reset_end cortex_a710, ERRATUM(2055002) 86 87check_erratum_ls cortex_a710, ERRATUM(2055002), CPU_REV(2, 0) 88 89workaround_reset_start cortex_a710, ERRATUM(2058056), ERRATA_A710_2058056 90 mrs x1, CORTEX_A710_CPUECTLR2_EL1 91 mov x0, #CORTEX_A710_CPUECTLR2_EL1_PF_MODE_CNSRV 92 bfi x1, x0, #CPUECTLR2_EL1_PF_MODE_LSB, #CPUECTLR2_EL1_PF_MODE_WIDTH 93 msr CORTEX_A710_CPUECTLR2_EL1, x1 94workaround_reset_end cortex_a710, ERRATUM(2058056) 95 96check_erratum_ls cortex_a710, ERRATUM(2058056), CPU_REV(2, 0) 97 98workaround_reset_start cortex_a710, ERRATUM(2081180), ERRATA_A710_2081180 99 ldr x0,=0x3 100 msr S3_6_c15_c8_0,x0 101 ldr x0,=0xF3A08002 102 msr S3_6_c15_c8_2,x0 103 ldr x0,=0xFFF0F7FE 104 msr S3_6_c15_c8_3,x0 105 ldr x0,=0x10002001003FF 106 msr S3_6_c15_c8_1,x0 107 ldr x0,=0x4 108 msr S3_6_c15_c8_0,x0 109 ldr x0,=0xBF200000 110 msr S3_6_c15_c8_2,x0 111 ldr x0,=0xFFEF0000 112 msr S3_6_c15_c8_3,x0 113 ldr x0,=0x10002001003F3 114 msr S3_6_c15_c8_1,x0 115workaround_reset_end cortex_a710, ERRATUM(2081180) 116 117check_erratum_ls cortex_a710, ERRATUM(2081180), CPU_REV(2, 0) 118 119workaround_reset_start cortex_a710, ERRATUM(2083908), ERRATA_A710_2083908 120 mrs x1, CORTEX_A710_CPUACTLR5_EL1 121 orr x1, x1, CORTEX_A710_CPUACTLR5_EL1_BIT_13 122 msr CORTEX_A710_CPUACTLR5_EL1, x1 123workaround_reset_end cortex_a710, ERRATUM(2083908) 124 125check_erratum_range cortex_a710, ERRATUM(2083908), CPU_REV(2, 0), CPU_REV(2, 0) 126 127workaround_reset_start cortex_a710, ERRATUM(2136059), ERRATA_A710_2136059 128 mrs x1, CORTEX_A710_CPUACTLR5_EL1 129 orr x1, x1, CORTEX_A710_CPUACTLR5_EL1_BIT_44 130 msr CORTEX_A710_CPUACTLR5_EL1, x1 131workaround_reset_end cortex_a710, ERRATUM(2136059) 132 133check_erratum_ls cortex_a710, ERRATUM(2136059), CPU_REV(2, 0) 134 135workaround_reset_start cortex_a710, ERRATUM(2147715), ERRATA_A710_2147715 136 mrs x1, CORTEX_A710_CPUACTLR_EL1 137 orr x1, x1, CORTEX_A710_CPUACTLR_EL1_BIT_22 138 msr CORTEX_A710_CPUACTLR_EL1, x1 139workaround_reset_end cortex_a710, ERRATUM(2147715) 140 141check_erratum_range cortex_a710, ERRATUM(2147715), CPU_REV(2, 0), CPU_REV(2, 0) 142 143workaround_reset_start cortex_a710, ERRATUM(2216384), ERRATA_A710_2216384 144 mrs x1, CORTEX_A710_CPUACTLR5_EL1 145 orr x1, x1, CORTEX_A710_CPUACTLR5_EL1_BIT_17 146 msr CORTEX_A710_CPUACTLR5_EL1, x1 147 148 ldr x0,=0x5 149 msr CORTEX_A710_CPUPSELR_EL3, x0 150 ldr x0,=0x10F600E000 151 msr CORTEX_A710_CPUPOR_EL3, x0 152 ldr x0,=0x10FF80E000 153 msr CORTEX_A710_CPUPMR_EL3, x0 154 ldr x0,=0x80000000003FF 155 msr CORTEX_A710_CPUPCR_EL3, x0 156workaround_reset_end cortex_a710, ERRATUM(2216384) 157 158check_erratum_ls cortex_a710, ERRATUM(2216384), CPU_REV(2, 0) 159 160workaround_reset_start cortex_a710, ERRATUM(2267065), ERRATA_A710_2267065 161 mrs x1, CORTEX_A710_CPUACTLR_EL1 162 orr x1, x1, CORTEX_A710_CPUACTLR_EL1_BIT_22 163 msr CORTEX_A710_CPUACTLR_EL1, x1 164workaround_reset_end cortex_a710, ERRATUM(2267065) 165 166check_erratum_ls cortex_a710, ERRATUM(2267065), CPU_REV(2, 0) 167 168workaround_reset_start cortex_a710, ERRATUM(2282622), ERRATA_A710_2282622 169 mrs x1, CORTEX_A710_CPUACTLR2_EL1 170 orr x1, x1, #BIT(0) 171 msr CORTEX_A710_CPUACTLR2_EL1, x1 172workaround_reset_end cortex_a710, ERRATUM(2282622) 173 174check_erratum_ls cortex_a710, ERRATUM(2282622), CPU_REV(2, 1) 175 176workaround_runtime_start cortex_a710, ERRATUM(2291219), ERRATA_A710_2291219 177 /* Set bit 36 in ACTLR2_EL1 */ 178 mrs x1, CORTEX_A710_CPUACTLR2_EL1 179 orr x1, x1, #CORTEX_A710_CPUACTLR2_EL1_BIT_36 180 msr CORTEX_A710_CPUACTLR2_EL1, x1 181workaround_runtime_end cortex_a710, ERRATUM(2291219), NO_ISB 182 183check_erratum_ls cortex_a710, ERRATUM(2291219), CPU_REV(2, 0) 184 185/* 186 * ERRATA_DSU_2313941 is defined in dsu_helpers.S but applies to Cortex-A710 as 187 * well. Create a symbollic link to existing errata workaround to get them 188 * registered under the Errata Framework. 189 */ 190.equ check_erratum_cortex_a710_2313941, check_errata_dsu_2313941 191.equ erratum_cortex_a710_2313941_wa, errata_dsu_2313941_wa 192add_erratum_entry cortex_a710, ERRATUM(2313941), ERRATA_DSU_2313941, APPLY_AT_RESET 193 194workaround_reset_start cortex_a710, ERRATUM(2371105), ERRATA_A710_2371105 195 /* Set bit 40 in CPUACTLR2_EL1 */ 196 mrs x1, CORTEX_A710_CPUACTLR2_EL1 197 orr x1, x1, #CORTEX_A710_CPUACTLR2_EL1_BIT_40 198 msr CORTEX_A710_CPUACTLR2_EL1, x1 199workaround_reset_end cortex_a710, ERRATUM(2371105) 200 201check_erratum_ls cortex_a710, ERRATUM(2371105), CPU_REV(2, 0) 202 203workaround_runtime_start cortex_a710, ERRATUM(2768515), ERRATA_A710_2768515 204 /* dsb before isb of power down sequence */ 205 dsb sy 206workaround_runtime_end cortex_a710, ERRATUM(2768515), NO_ISB 207 208check_erratum_ls cortex_a710, ERRATUM(2768515), CPU_REV(2, 1) 209 210workaround_reset_start cortex_a710, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 211#if IMAGE_BL31 212 /* 213 * The Cortex-A710 generic vectors are overridden to apply errata 214 * mitigation on exception entry from lower ELs. 215 */ 216 adr x0, wa_cve_vbar_cortex_a710 217 msr vbar_el3, x0 218#endif /* IMAGE_BL31 */ 219workaround_reset_end cortex_a710, CVE(2022, 23960) 220 221check_erratum_chosen cortex_a710, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 222 223 /* ---------------------------------------------------- 224 * HW will do the cache maintenance while powering down 225 * ---------------------------------------------------- 226 */ 227func cortex_a710_core_pwr_dwn 228 apply_erratum cortex_a710, ERRATUM(2008768), ERRATA_A710_2008768 229 apply_erratum cortex_a710, ERRATUM(2291219), ERRATA_A710_2291219, NO_GET_CPU_REV 230 231 /* --------------------------------------------------- 232 * Enable CPU power down bit in power control register 233 * --------------------------------------------------- 234 */ 235 sysreg_bit_set CORTEX_A710_CPUPWRCTLR_EL1, CORTEX_A710_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 236 apply_erratum cortex_a710, ERRATUM(2768515), ERRATA_A710_2768515, NO_GET_CPU_REV 237 isb 238 ret 239endfunc cortex_a710_core_pwr_dwn 240 241errata_report_shim cortex_a710 242 243cpu_reset_func_start cortex_a710 244 /* Disable speculative loads */ 245 msr SSBS, xzr 246cpu_reset_func_end cortex_a710 247 248 /* --------------------------------------------- 249 * This function provides Cortex-A710 specific 250 * register information for crash reporting. 251 * It needs to return with x6 pointing to 252 * a list of register names in ascii and 253 * x8 - x15 having values of registers to be 254 * reported. 255 * --------------------------------------------- 256 */ 257.section .rodata.cortex_a710_regs, "aS" 258cortex_a710_regs: /* The ascii list of register names to be reported */ 259 .asciz "cpuectlr_el1", "" 260 261func cortex_a710_cpu_reg_dump 262 adr x6, cortex_a710_regs 263 mrs x8, CORTEX_A710_CPUECTLR_EL1 264 ret 265endfunc cortex_a710_cpu_reg_dump 266 267declare_cpu_ops cortex_a710, CORTEX_A710_MIDR, \ 268 cortex_a710_reset_func, \ 269 cortex_a710_core_pwr_dwn 270