Merge "build(dev-deps): bump js-yaml in the dev-deps group across 1 directory" into integration

feat(rcar): add initial BL31 support for Renesas R-Car X5H

This patch introduces initial BL31 (EL3 firmware) support for the
Renesas R-Car Gen5 (X5H) platform.

Key features and changes include:
- P

feat(rcar): add initial BL31 support for Renesas R-Car X5H

This patch introduces initial BL31 (EL3 firmware) support for the
Renesas R-Car Gen5 (X5H) platform.

Key features and changes include:
- Platform definitions and memory map for R-Car X5H
(Cortex-A720AE, 8 clusters x 4 cores)
- Platform-specific PSCI power management and topology
- SCMI-based power domain and system power management
- GICv4/Fainlight-AE interrupt controller initialization and support
- Trusted SRAM, shared memory, and crash log region setup
- SCIF console support
- Stack protector implementation for enhanced security
- Platform-specific linker script and build integration
- Various helper and initialization routines for MMU, GIC, and SCMI
- Platform-specific mailbox and boot flow handling
- Basic suspend implementation via SCP-FW
- AMU counters, SVE, PAUTH accessible to EL1

Signed-off-by: Hieu Nguyen <hieu.nguyen.dn@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Change-Id: I04be48a55a618fe952b28283d2f85f48f7761c9a

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Merge "fix(cpufeat): require FEAT_AMUv1p1 to enable the auxiliary counters" into integration

docs(threat-model): clarify scope of experimental features

Experimental features are out of the scope of TF-A threat model. This
is stated in the "Generic Threat Model" [1] document for example but

docs(threat-model): clarify scope of experimental features

Experimental features are out of the scope of TF-A threat model. This
is stated in the "Generic Threat Model" [1] document for example but
not in some of the other threat model documents. To remove any
ambiguity, state this in the top-level threat model indexing page [2]
so it's clear this applies to all configurations of TF-A.

[1] https://trustedfirmware-a.readthedocs.io/en/latest/threat_model/firmware_threat_model/threat_model.html
[2] https://trustedfirmware-a.readthedocs.io/en/latest/threat_model/firmware_threat_model/index.html

Change-Id: I8c1db95ff32dd33c9374fb159b2c8cf4da5fdc20
Signed-off-by: Sandrine Afsa <sandrine.afsa@arm.com>

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Merge "feat(build): enable link-time optimization by default" into integration

Merge "fix(gicv5): align IWB_WDOMAINR to the EAC spec" into integration

feat(build): enable link-time optimization by default

Enable LTO by default for all platforms and compilers. LTO performs
optimisation at link-time rather than at compilation time, and allows
optimi

feat(build): enable link-time optimization by default

Enable LTO by default for all platforms and compilers. LTO performs
optimisation at link-time rather than at compilation time, and allows
optimisations to be made across compilation unit boundaries (i.e. C
files). This is especially useful in areas with lots of closely related
compilation units that operate on the same data structures (eg PSCI and
context management).

The only drawback is that LTO makes conditions ripe for the build to
heavily mangle all functions, making debugging a nightmare. So only
enable for release builds.

Note this will make object files unintepretable by objdump. Use lto-dump
instead.

BREAKING-CHANGE: LTO has been enabled by default, which may cause
unpredictable issues for platforms where the linker scripts have not
been designed with LTO in mind. Please report any issues to the
[mailing list](mailto:tf-a@lists.trustedfirmware.org).

Change-Id: Ia472aff1a23366d918abded7a1c5da695f2c4787
Co-authored-by: Chris Kay <chris.kay@arm.com>
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(psci): get the cpu_ops before exiting coherency

It is possible for the cpu_data structure to be cached somewhere in the
cache hierarchy. When HW_ASSISTED_COHERENCY == 0 we flush the core's
priva

fix(psci): get the cpu_ops before exiting coherency

It is possible for the cpu_data structure to be cached somewhere in the
cache hierarchy. When HW_ASSISTED_COHERENCY == 0 we flush the core's
private caches (usually the L1). However, the destination might be
shared caches (eg DSU L2 cache) so when we subsequently dereference the
cpu_data pointer we could get a stale value.

So dereference it prior to disabling the caches to avoid this scenario
and do all accesses from a coherent view of memory.

Change-Id: If118ca8c0436dd04d6ad0d57073d69305a7f41cb
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(neoverse-rd): set the correct Arm version for rdn2

The neoverse N2 and V2 cores in use on the platform are both v9
compliant. Declare the ARM_ARCH_{MAJOR, MINOR} to reflect this.

Change-Id: I1

feat(neoverse-rd): set the correct Arm version for rdn2

The neoverse N2 and V2 cores in use on the platform are both v9
compliant. Declare the ARM_ARCH_{MAJOR, MINOR} to reflect this.

Change-Id: I15556fde3740056b1eb81138d19635b507064abf
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge changes I6e44c7f1,Id4320cbf,Ibb05dd47,Icec70861 into integration

* changes:
fix(morello): don't define get_mem_client_mode() when it won't be used
fix(rdn2): don't use V1 as a label
fix(

Merge changes I6e44c7f1,Id4320cbf,Ibb05dd47,Icec70861 into integration

* changes:
fix(morello): don't define get_mem_client_mode() when it won't be used
fix(rdn2): don't use V1 as a label
fix(tspd): don't forward declare tsp_vectors_t
fix(cpufeat): drop feature_panic() as unused

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fix(cpufeat): require FEAT_AMUv1p1 to enable the auxiliary counters

The auxiliary counters are a feature of FEAT_AMUv1p1 but it's possible
to enable them (ENABLE_AMU_AUXILIARY_COUNTERS=1) without en

fix(cpufeat): require FEAT_AMUv1p1 to enable the auxiliary counters

The auxiliary counters are a feature of FEAT_AMUv1p1 but it's possible
to enable them (ENABLE_AMU_AUXILIARY_COUNTERS=1) without enabling
FEAT_AMUv1p1. As a result, the AMU_RESTRICT_COUNTERS may not take
effect, making this configuration potentially insecure.

Fix this by adding a constraints and rejigging auxiliary counter enables
such that they only happen when FEAT_AMUv1p1 has been enabled so that's
more apparent.

Change-Id: I5b5061d603013598f07d70401d68915c016a1a1b
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(s32g274ardb): add DDR register accessories

Introduce a set of helper functions that
simplify register reads, bitfield updates,
AXI parity configuration and extraction
of training values.

These

feat(s32g274ardb): add DDR register accessories

Introduce a set of helper functions that
simplify register reads, bitfield updates,
AXI parity configuration and extraction
of training values.

These utilities encapsulate register access
patterns and are used for delay calibration,
Vref averaging, memory type detection and PLL
source selection.

Change-Id: I5415a650f6430578a8cca13ff7e144b471c61466
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Signed-off-by: Andrei Cherechesu <andrei.cherechesu@nxp.com>
Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@nxp.com>

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feat(s32g274ardb): add DDR PHY mailbox support

Introduce mailbox handling between the DDR
controller and the PHY firmware, providing
mechanisms for message exchange, acknowledgments,
and execution s

feat(s32g274ardb): add DDR PHY mailbox support

Introduce mailbox handling between the DDR
controller and the PHY firmware, providing
mechanisms for message exchange, acknowledgments,
and execution status monitoring.

This enables reliable tracking of firmware
progress during DDR initialization and training,

Change-Id: I4fdd582fcc9a88c09c820ce9e59fe14ec3c043a8
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Signed-off-by: Andrei Cherechesu <andrei.cherechesu@nxp.com>
Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@nxp.com>

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fix(gicv5): align IWB_WDOMAINR to the EAC spec

The offset changed from 0x6000 to 0x8000.

Change-Id: I3a95e16c5379e2bb200a1ffaf40e3bae73288c5a
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

Merge "docs(changelog): changelog for v2.14 release" into integration

Merge "docs: update specification link in readme" into integration

docs: update specification link in readme

Change outdated links to the latest documentation for
PSCI, SMC Calling Convention, SCMI, and SDEI to ensure users have
access to the most current resources

docs: update specification link in readme

Change outdated links to the latest documentation for
PSCI, SMC Calling Convention, SCMI, and SDEI to ensure users have
access to the most current resources.

Change-Id: I2ee689d179a5d3ef96b55c45f52ace645ab52eb0
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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docs(changelog): changelog for v2.14 release

Generated this change-log using below command:
npm run release -- --skip.commit --skip.tag --release-as 2.14.0

Signed-off-by: Arvind Ram Prakash <arvind

docs(changelog): changelog for v2.14 release

Generated this change-log using below command:
npm run release -- --skip.commit --skip.tag --release-as 2.14.0

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I3745f4506de123e3a4ff1e3ca6d5992f3b5c174a

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Merge "fix(changelog): fix platform order and add smcc to deprecated" into integration

fix(changelog): fix platform order and add smcc to deprecated

Some platforms were not added in alphabetical order
and this patch fixes it. This patch also deprecates
the scope "smcc".

Signed-off-by

fix(changelog): fix platform order and add smcc to deprecated

Some platforms were not added in alphabetical order
and this patch fixes it. This patch also deprecates
the scope "smcc".

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: Ieea2d49ab7d24377edad840f25af563f38ac7e41

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Merge "docs(n1sdp): update PSCI instrumentation data" into integration

docs(n1sdp): update PSCI instrumentation data

Update for v2.14 release based on v2.14-rc0

Change-Id: I74461f8ff009384c7db64a0a7f5b67a071a53334
Signed-off-by: Slava Andrianov <slava.andrianov@arm.co

docs(n1sdp): update PSCI instrumentation data

Update for v2.14 release based on v2.14-rc0

Change-Id: I74461f8ff009384c7db64a0a7f5b67a071a53334
Signed-off-by: Slava Andrianov <slava.andrianov@arm.com>

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Merge "feat(handoff): add firmware handoff threat model" into integration

feat(handoff): add firmware handoff threat model

Add threat model covering the Transfer List library (libTL) which
provides TF-A's implementation of the firmware handoff framework.

Change-Id: Idac6

feat(handoff): add firmware handoff threat model

Add threat model covering the Transfer List library (libTL) which
provides TF-A's implementation of the firmware handoff framework.

Change-Id: Idac6d5d423ed95bc4f0460a80007fd8d45976b19
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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Merge "docs: remove RME out of box testing instructions" into integration