| 9013bf2f | 03-Dec-2025 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge "fix(tc): correct register write in rng trap handler" into integration |
| e0e5a311 | 03-Dec-2025 |
Yann Gautier <yann.gautier@st.com> |
Merge "fix(rcar5): enable missing FEAT_AMUv1p1 on R-Car Gen5 to fix the build" into integration |
| a00fee77 | 02-Dec-2025 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
fix(rcar5): enable missing FEAT_AMUv1p1 on R-Car Gen5 to fix the build
Since commit 6edbd2d6a8ae ("fix(cpufeat): require FEAT_AMUv1p1 to
enable the auxiliary counters") the ENABLE_AMU_AUXILIARY_COUN
fix(rcar5): enable missing FEAT_AMUv1p1 on R-Car Gen5 to fix the build
Since commit 6edbd2d6a8ae ("fix(cpufeat): require FEAT_AMUv1p1 to
enable the auxiliary counters") the ENABLE_AMU_AUXILIARY_COUNTERS
requires ENABLE_FEAT_AMUv1p1 to be enabled as well. Enable missing
ENABLE_FEAT_AMUv1p1 to fix the build, which was broken because the
R-Car Gen5 and FEAT_AMUv1p1 commits landed in reverse order.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Change-Id: I834aff7798d7a5e10014fbd9f1ac8a97908b9aab
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| 7cab2c23 | 02-Dec-2025 |
Govindraj Raja <govindraj.raja@arm.com> |
Merge "feat(rcar): add initial BL31 support for Renesas R-Car X5H" into integration |
| 22b9c02f | 02-Dec-2025 |
Mark Dykes <mark.dykes@arm.com> |
Merge "fix(intel): allow kernel access to TSN TBU stream control registers" into integration |
| 20187408 | 02-Dec-2025 |
Govindraj Raja <govindraj.raja@arm.com> |
Merge "fix: remove circular dependency on ENABLE_FEAT_RAS" into integration |
| e9f69b9f | 02-Dec-2025 |
Kamlesh Gurudasani <kamlesh@ti.com> |
feat(clk): add get_possible_parents_num callback
This callback will be used to get number of possible parents if
the underlying clock driver supports this option.
Change-Id: I9459c878dd2155ff24b72c
feat(clk): add get_possible_parents_num callback
This callback will be used to get number of possible parents if
the underlying clock driver supports this option.
Change-Id: I9459c878dd2155ff24b72cef6851180e105be432
Signed-off-by: Kamlesh Gurudasani <kamlesh@ti.com>
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| bacd68ff | 01-Dec-2025 |
Mark Dykes <mark.dykes@arm.com> |
Merge "fix(libfdt): fix coverity reported issue" into integration |
| 894b7b2c | 01-Dec-2025 |
Mark Dykes <mark.dykes@arm.com> |
Merge changes from topic "gr/cov_fixes" into integration
* changes:
fix(libc): fix coverity deadcode issue
fix(zlib): fix overflow issue from coverity |
| 02b22a5a | 01-Dec-2025 |
Govindraj Raja <govindraj.raja@arm.com> |
Merge changes from topic "tc-lsc-25-cpu-libs" into integration
* changes:
feat(cpus): add support for LSC25 E-core CPU
feat(cpus): add support for LSC25 P-core CPU |
| 4fdabe02 | 01-Dec-2025 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge "feat(crypto): enable SIMD crypto extensions for S-EL1" into integration |
| 4286d16f | 26-Nov-2025 |
Arvind Ram Prakash <arvind.ramprakash@arm.com> |
feat(cpufeat): add support for FEAT_UINJ
FEAT_UINJ allows higher ELs to inject Undefined Instruction exceptions
into lower ELs by setting SPSR_ELx.UINJ, which updates PSTATE.UINJ on
exception return
feat(cpufeat): add support for FEAT_UINJ
FEAT_UINJ allows higher ELs to inject Undefined Instruction exceptions
into lower ELs by setting SPSR_ELx.UINJ, which updates PSTATE.UINJ on
exception return. When PSTATE.UINJ is set, instruction execution at the
lower EL raises an Undefined Instruction exception (EC=0b000000).
This patch introduces support for FEAT_UINJ by updating the
inject_undef64() to use hardware undef injection if supported.
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I48ad56a58eaab7859d508cfa8dfe81130b873b6b
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| 9838436c | 26-Nov-2025 |
Arvind Ram Prakash <arvind.ramprakash@arm.com> |
feat(cpufeat): enable mandatory Armv9.4–Armv9.6 features by default
This patch sets Armv9.4-Armv9.6 mandatory features
to 1 by default.
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
feat(cpufeat): enable mandatory Armv9.4–Armv9.6 features by default
This patch sets Armv9.4-Armv9.6 mandatory features
to 1 by default.
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I12382e8765f3af7a5428abb1cf1ea0407fdd3849
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| 3a6e53c8 | 11-Nov-2025 |
Arvind Ram Prakash <arvind.ramprakash@arm.com> |
fix(cpufeat): update feature names and comments
Fix supported feature list for FEAT_CSV2_2/CSV2_3 and add clearer
descriptions for LS64_ACCDATA, AIE, and PFAR features.
Signed-off-by: Arvind Ram Pr
fix(cpufeat): update feature names and comments
Fix supported feature list for FEAT_CSV2_2/CSV2_3 and add clearer
descriptions for LS64_ACCDATA, AIE, and PFAR features.
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I0073db4007b90e4a37c337af789a7f5c98677372
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| 3ca44b82 | 11-Nov-2025 |
Arvind Ram Prakash <arvind.ramprakash@arm.com> |
fix(cpufeat): simplify AArch32 feature disablement
Remove redundant conditional checks for unsupported features
(SPE, SVE, MPAM) in aarch32 builds and set them unconditionally
to 0. Add correspondin
fix(cpufeat): simplify AArch32 feature disablement
Remove redundant conditional checks for unsupported features
(SPE, SVE, MPAM) in aarch32 builds and set them unconditionally
to 0. Add corresponding constraint checks to ensure these
features are not enabled when ARCH=aarch32.
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I6486b54c69bf0c273371235d1661fafbcb7abb8c
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| 17511817 | 01-Dec-2025 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge "fix(gpt): remove unused `gpt_disable` function" into integration |
| 3f8cf8a1 | 16-Oct-2025 |
Xialin Liu <xialin.liu@arm.com> |
feat(crypto): enable SIMD crypto extensions for S-EL1
Enable the SIMD in arch setup to enable SIMD crypto
extension for S-EL1 for BL2
Change-Id: I5573b5f214ca5d520ee45b380375df4c2344acf1
Signed-off
feat(crypto): enable SIMD crypto extensions for S-EL1
Enable the SIMD in arch setup to enable SIMD crypto
extension for S-EL1 for BL2
Change-Id: I5573b5f214ca5d520ee45b380375df4c2344acf1
Signed-off-by: Xialin Liu <xialin.liu@arm.com>
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| 30c4248d | 01-Dec-2025 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "fix(psci): get the cpu_ops before exiting coherency" into integration |
| b0236d0a | 01-Dec-2025 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge changes I1eb8d262,I8e3e0ce6 into integration
* changes:
docs(arm): document BL2 mem params override
feat(arm): allow custom BL2 mem params |
| 905747ef | 15-Nov-2025 |
Ahmed Azeem <ahmed.azeem@arm.com> |
docs(arm): document BL2 mem params override
Add documentation for the ARM_PLAT_PROVIDES_BL2_MEM_PARAMS flag,
which allows platforms to supply their own
bl2_mem_params_desc.c implementation instead o
docs(arm): document BL2 mem params override
Add documentation for the ARM_PLAT_PROVIDES_BL2_MEM_PARAMS flag,
which allows platforms to supply their own
bl2_mem_params_desc.c implementation instead of using the common
Arm platform implementation.
Change-Id: I1eb8d262ba404f10a3cc2a0ff23bbc3f70041115
Signed-off-by: Ahmed Azeem <ahmed.azeem@arm.com>
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| 7622cecc | 15-Nov-2025 |
Ahmed Azeem <ahmed.azeem@arm.com> |
feat(arm): allow custom BL2 mem params
Introduce the ARM_PLAT_PROVIDES_BL2_MEM_PARAMS flag so that
Arm platforms can supply their own bl2_mem_params_desc.c
implementation if needed. When this overri
feat(arm): allow custom BL2 mem params
Introduce the ARM_PLAT_PROVIDES_BL2_MEM_PARAMS flag so that
Arm platforms can supply their own bl2_mem_params_desc.c
implementation if needed. When this override is enabled,
the common arm_bl2_mem_params_desc.c implementation is
excluded from BL2_SOURCES. The platform must then append
its own bl2_mem_params_desc.c file to BL2_SOURCES.
Change-Id: I8e3e0ce6e9c2c55ec3feb18a45890f1716fe690b
Signed-off-by: Ahmed Azeem <ahmed.azeem@arm.com>
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| 39772b5f | 01-Dec-2025 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge changes I49097cc1,Iad299bf9 into integration
* changes:
docs(rdaspen): measured boot support
feat(rdaspen): enable measured boot |
| 764e2bd9 | 24-Nov-2025 |
Ludovic Mermod <ludovic.mermod@arm.com> |
fix(gpt): remove unused `gpt_disable` function
After GPT protections are enabled, there are no scenarios where they
need to be disabled, similarly to how TZC-400 protections are not
disabled after b
fix(gpt): remove unused `gpt_disable` function
After GPT protections are enabled, there are no scenarios where they
need to be disabled, similarly to how TZC-400 protections are not
disabled after being setup.
Change-Id: I7eae3147130c7a6c3b7b3e9c10e8e7229f32505d
Signed-off-by: Ludovic Mermod <ludovic.mermod@arm.com>
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| 06ebb61d | 11-Nov-2025 |
Maximilian Berndt <maximilian.berndt@arm.com> |
docs(rdaspen): measured boot support
Add optional measured boot support for RDaspen platform to enable
image and data measurement.
Change-Id: I49097cc1bbbda3c96a6ca22f1e7e76087b3ee856
Signed-off-by
docs(rdaspen): measured boot support
Add optional measured boot support for RDaspen platform to enable
image and data measurement.
Change-Id: I49097cc1bbbda3c96a6ca22f1e7e76087b3ee856
Signed-off-by: Maximilian Berndt <maximilian.berndt@arm.com>
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| 0bf4d2bc | 08-May-2025 |
Maximilian Berndt <maximilian.berndt@arm.com> |
feat(rdaspen): enable measured boot
Ports functions to support measured boot.
Additionally, add AP BL31, BL32 and BL33 to list of measured images.
Change-Id: Iad299bf902833c5472dce7eb1344f59d73a16f
feat(rdaspen): enable measured boot
Ports functions to support measured boot.
Additionally, add AP BL31, BL32 and BL33 to list of measured images.
Change-Id: Iad299bf902833c5472dce7eb1344f59d73a16f91
Signed-off-by: Maximilian Berndt <maximilian.berndt@arm.com>
Signed-off-by: Ahmed Azeem <ahmed.azeem@arm.com>
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