fix(zynqmp): add const qualifier

This correct the MISRA violation C2012-8.13:
A pointer should point to a const-qualified type whenever possible.
Added const qualifier to pointer in the function arg

fix(zynqmp): add const qualifier

This correct the MISRA violation C2012-8.13:
A pointer should point to a const-qualified type whenever possible.
Added const qualifier to pointer in the function arguments.

Change-Id: If1f86a01a8bcd7f9be48b5ca3a6a00df439f2fab
Signed-off-by: Nithin G <nithing@amd.com>
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

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fix(rockchip): fix "unexpected token" error with clang

Change-Id: I5be872c882801d170af4511b2289b77a13395162
Signed-off-by: mojyack <mojyack@gmail.com>

Merge changes from topic "xlnx_versal2_changes" into integration

* changes:
feat(versal2): support dynamic XLAT tables
fix(versal2): update check for TRANSFER_LIST macro

fix(tc): retain NS timer frame ID for TC2 as 0

Recent change [1], caused failure in the TC2 run and this
change meant to be for TC3 and TC4.

[1]: https://review.trustedfirmware.org/c/TF-A/trusted-f

fix(tc): retain NS timer frame ID for TC2 as 0

Recent change [1], caused failure in the TC2 run and this
change meant to be for TC3 and TC4.

[1]: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/31424

Change-Id: Ibfd604a842815bcf6d413dcba2c440df81dbb486
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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Merge "feat(context-mgmt): introduce EL3/root context" into integration

fix(brbe): allow RME builds with BRBE

It used to be the case that a FEAT_RME build could not be built with
FEAT_BRBE support. BRBE doesn't have a 3-world aware disable and
MDCR_EL3 was not context s

fix(brbe): allow RME builds with BRBE

It used to be the case that a FEAT_RME build could not be built with
FEAT_BRBE support. BRBE doesn't have a 3-world aware disable and
MDCR_EL3 was not context switched to allow for disabling in Realm world.

As of commit 123002f9171384d976d95935b7f566740d69cc68 MDCR_EL3 is
context switched. Since the flag for BRBE support is
ENABLE_BRBE_FOR_NS, move brbe_enable() to only happen for NS world. The
other worlds will see BRBE disabled and branch recording prohibited.
This allows for a build with both RME and BRBE.

Note that EL2 BRBE registers are not context switched. Further work is
needed if non-NS support is required.

Change-Id: I82f0f08399dcd080902477dc9636bc4541685f89
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge changes I7d9444d5,I7b104c8e into integration

* changes:
feat(mt8192): update memory protect region
feat(mt8195): update memory protect region

feat(versal2): support dynamic XLAT tables

Enable support for Dynamic XLAT Tables by default for
AMD Versal Gen 2 Platform.

Change-Id: I532d9b208b0e7d8a7b1ffad741cc6c1cec0bd2ab
Signed-off-by: Aksha

feat(versal2): support dynamic XLAT tables

Enable support for Dynamic XLAT Tables by default for
AMD Versal Gen 2 Platform.

Change-Id: I532d9b208b0e7d8a7b1ffad741cc6c1cec0bd2ab
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>

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fix(versal2): update check for TRANSFER_LIST macro

Replace #if defined(TRANSFER_LIST) by #if TRANSFER_LIST.
By default TRANSFER_LIST macro is defined with value 0 in Makefile.
So checking if the mac

fix(versal2): update check for TRANSFER_LIST macro

Replace #if defined(TRANSFER_LIST) by #if TRANSFER_LIST.
By default TRANSFER_LIST macro is defined with value 0 in Makefile.
So checking if the macro is defined will always be true and instead
need to check the value of the macro to add the conditional code.

Change-Id: I90b06f378326d5e03ad576377ad173e81b100f56
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>

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Merge changes from topic "xlnx_fix_eval_bool" into integration

* changes:
fix(versal_net): evaluate condition for boolean
fix(versal): evaluate condition for boolean
fix(zynqmp): evaluate cond

Merge changes from topic "xlnx_fix_eval_bool" into integration

* changes:
fix(versal_net): evaluate condition for boolean
fix(versal): evaluate condition for boolean
fix(zynqmp): evaluate condition for boolean
fix(xilinx): rename variable to avoid conflict

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Merge "fix(intel): implement soc and lwsoc bridge control for burst speed" into integration

Merge "feat(intel): update hand-off data to include agilex5 params" into integration

fix(intel): implement soc and lwsoc bridge control for burst speed

Implement burst speed read/write for SOC and LWSOC. Set bridge control
register to enable the register bit

Change-Id: I815b912cb90

fix(intel): implement soc and lwsoc bridge control for burst speed

Implement burst speed read/write for SOC and LWSOC. Set bridge control
register to enable the register bit

Change-Id: I815b912cb90d79a548163d198eea177d70dfbc0d
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

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feat(intel): update hand-off data to include agilex5 params

Update hand-off data structure to include agilex5
platform specific parameters.

Change-Id: Ic610e2d8da7488e49462293d13293e26520579e2
Sign

feat(intel): update hand-off data to include agilex5 params

Update hand-off data structure to include agilex5
platform specific parameters.

Change-Id: Ic610e2d8da7488e49462293d13293e26520579e2
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

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Merge "fix(intel): update mailbox SDM printout message" into integration

Merge "fix(intel): update the size with addition 0x8000 0000 base" into integration

Merge "refactor(delay-timer): add timer callback functions" into integration

feat(cpus): add support for arcadia cpu

Add basic CPU library code to support the Arcadia CPU.

Change-Id: Iecb0634dc6dcb34e9b5fda4902335530d237cc43
Signed-off-by: Govindraj Raja <govindraj.raja@arm

feat(cpus): add support for arcadia cpu

Add basic CPU library code to support the Arcadia CPU.

Change-Id: Iecb0634dc6dcb34e9b5fda4902335530d237cc43
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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Merge "fix(intel): fix bridge enable and disable function" into integration

Merge "fix(intel): update outdated code for Linux direct boot" into integration

Merge "fix(intel): update Agilex5 BL2 init flow and other misc changes" into integration

Merge "feat(intel): update Agilex5 DDR and IOSSM driver" into integration

fix(intel): update the size with addition 0x8000 0000 base

The FPGA_CONFIG_SIZE is actually the end address of FPGA_CONFIG_ADDR
Thus, we need to add in the DDR base address which is 0x8000 0000.

Ch

fix(intel): update the size with addition 0x8000 0000 base

The FPGA_CONFIG_SIZE is actually the end address of FPGA_CONFIG_ADDR
Thus, we need to add in the DDR base address which is 0x8000 0000.

Change-Id: I177596243e0616c6eadc2fa388e85e28692dc8f7
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

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fix(intel): fix bridge enable and disable function

1. hps reset and reboot spec is missing ack clear status step
2. software workaround for bridge timeout
3. f2sdram bridge quick write thru failed
4

fix(intel): fix bridge enable and disable function

1. hps reset and reboot spec is missing ack clear status step
2. software workaround for bridge timeout
3. f2sdram bridge quick write thru failed
4. bridge timeout workaround for F2SOC and F2SDRAM


Change-Id: Ide4210ff862531f82e083633af385b559ffbe16b
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

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fix(intel): update outdated code for Linux direct boot

1. Update emif rsthdshk macro
2. Update mailbox return status
3. Update bridge return status

Change-Id: I33905508aceb258ac8759c10079b2af977df

fix(intel): update outdated code for Linux direct boot

1. Update emif rsthdshk macro
2. Update mailbox return status
3. Update bridge return status

Change-Id: I33905508aceb258ac8759c10079b2af977df0e0a
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

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