fix(romlib): romlib build without MbedTLS

The ROMLIB build currently has a strong dependency on MbedTLS. This
patch has been introduced to remove this dependency, making it more
flexible.

Change-Id

fix(romlib): romlib build without MbedTLS

The ROMLIB build currently has a strong dependency on MbedTLS. This
patch has been introduced to remove this dependency, making it more
flexible.

Change-Id: If8c4cc7cf557687f40b235a4b8f931cfb70943fd
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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chore(romlib): remove unused jmptbl.i file

Remove the unused jmptbl.i file. The ROMLIB Makefile expects
platforms to provide the jmptbl according to their requirements.

Change-Id: I2784eaca5061aa77

chore(romlib): remove unused jmptbl.i file

Remove the unused jmptbl.i file. The ROMLIB Makefile expects
platforms to provide the jmptbl according to their requirements.

Change-Id: I2784eaca5061aa77fdd99f7b2b5ef5a1145475e9
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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Merge "fix(tc): replace vencoder with simple panel for kernel > 6.6" into integration

Merge "feat(cpus): add support for Alto CPU" into integration

fix(tc): replace vencoder with simple panel for kernel > 6.6

The component-aware simple encoder has become outdated with the latest
upstream DRM subsystem changes since Linux kernel commit 4cfe5cc02

fix(tc): replace vencoder with simple panel for kernel > 6.6

The component-aware simple encoder has become outdated with the latest
upstream DRM subsystem changes since Linux kernel commit 4cfe5cc02e3f
("drm/arm/komeda: Remove component framework and add a simple encoder")

To address this we introduce a new compilation flag
`TC_DPU_USE_SIMPLE_PANEL` for control panel vs. encoder enablement.
This flag is set when the kernel version is >= 6.6 and 0 when the kernel
version is < 6.6.

We also rename the `vencoder_in` node to `lcd_in` to avoid unnecessary
conditional code for vencoder vs. simple panel enablement.

Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>
Change-Id: Ibb14a56911cfb406b2181a22cc40db58d8ceaa8d

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feat(cpus): add support for Alto CPU

Add basic CPU library code to support the Alto CPU.

Change-Id: I45958be99c4a350a32a9e511d3705fb568b97236
Signed-off-by: Igor Podgainõi <igor.podgainoi@arm.com>

Merge changes I00d2de7b,I5ec82646 into integration

* changes:
feat(tc): fpga: Enable support for loading FIP image to DRAM
feat(tc): allow Android load and Boot From RAM

feat(tc): fpga: Enable support for loading FIP image to DRAM

This patch enable support for loading FIP image into DRAM rather than
flash drive.

Change-Id: I00d2de7b22e315db7f3e8a835ddd414ab297b554

feat(tc): fpga: Enable support for loading FIP image to DRAM

This patch enable support for loading FIP image into DRAM rather than
flash drive.

Change-Id: I00d2de7b22e315db7f3e8a835ddd414ab297b554
Signed-off-by: Vishnu Satheesh <vishnu.satheesh@arm.com>
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>

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feat(tc): allow Android load and Boot From RAM

This commit introduces the below changes:
* Define TC_FPGA_ANDROID_IMG_IN_RAM config variable
* Add phram node in dts.
* Memory configuration for loadi

feat(tc): allow Android load and Boot From RAM

This commit introduces the below changes:
* Define TC_FPGA_ANDROID_IMG_IN_RAM config variable
* Add phram node in dts.
* Memory configuration for loading Android image

Change-Id: I5ec82646cb2993e7b5976e702ebcc8efa51d1128
Signed-off-by: Vishnu Satheesh <vishnu.satheesh@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>

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Merge changes I04ecd50f,I830b53e2 into integration

* changes:
fix(rcar3-drivers): disable A/B loader support by default
fix(rcar-layout): fix tool build

Merge "chore(tc): enable the full 16GB DRAM for TC3 and TC4 as default" into integration

Merge "feat(tc): increase SCP BL2 size to support optimization 0" into integration

feat(intel): add support for query SDM config error and status

Currently the FPGA reconfig status only return a single error status
which make the debugging of FPGA reconfiguration hard.

This patch

feat(intel): add support for query SDM config error and status

Currently the FPGA reconfig status only return a single error status
which make the debugging of FPGA reconfiguration hard.

This patch is to expose the error status, major error code and
minor error code, for the FPGA reconfig to upper layer app.

Change-Id: I2fc68e30b45ff137f3e52f9569fdf2eaf2ca94ee
Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

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fix(rd1ae): fix rd1-ae device tree

Fix issues in RD1-AE flattened device tree source

- Update GIC GICR register region size to 0x40_0000.
GICR region size = 16 (RDcount) * 64KB frame size * 4 (wi

fix(rd1ae): fix rd1-ae device tree

Fix issues in RD1-AE flattened device tree source

- Update GIC GICR register region size to 0x40_0000.
GICR region size = 16 (RDcount) * 64KB frame size * 4 (with GIC v4.1)
- Update cpu_on function ID in psci node.
Use SMC64 version function ID 0xc4000003 instead. Although this
property doesn't actually take effect, align its value with
cpu_suspend selection to avoid any confusion.

Change-Id: Ib0840db45d32f0c8f1eb7dc74dc7d9b4ca6de0c3
Signed-off-by: David Hu <david.hu2@arm.com>

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Merge "feat(mt8196): add GPIO support" into integration

feat(tc): increase SCP BL2 size to support optimization 0

It requires at least 140 KB to support SCP BL2 optimization 0.
Increase the size to 192 KB (0x30000) considering space for growth.

Signed-o

feat(tc): increase SCP BL2 size to support optimization 0

It requires at least 140 KB to support SCP BL2 optimization 0.
Increase the size to 192 KB (0x30000) considering space for growth.

Signed-off-by: Tintu Thomas <tintu.thomas@arm.com>
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>
Change-Id: Ib416c89226475d44746a7561dd949a14349c3e4b

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feat(mt8196): add GPIO support

- MT8196 has 271 GPIO pins. Therefore, update id to a proper datatype.
- Add GPIO support for MT8196.

Signed-off-by: Cathy Xu <ot_cathy.xu@mediatek.com>
Change-Id: I2

feat(mt8196): add GPIO support

- MT8196 has 271 GPIO pins. Therefore, update id to a proper datatype.
- Add GPIO support for MT8196.

Signed-off-by: Cathy Xu <ot_cathy.xu@mediatek.com>
Change-Id: I283939684b54f79d1bba02f38e047e756a56f0c9

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fix(spmd): fix build failure due to redefinition

Clang build breaks with the following warning:

| In file included from services/std_svc/spmd/spmd_logical_sp.c:15:
| include/services/el3_spmd

fix(spmd): fix build failure due to redefinition

Clang build breaks with the following warning:

| In file included from services/std_svc/spmd/spmd_logical_sp.c:15:
| include/services/el3_spmd_logical_sp.h:15:38: error: redefinition of
| typedef 'spmd_spm_core_context_t' is a C11 feature [-Werror,-Wtypedef-redefinition].
| 15 | typedef struct spmd_spm_core_context spmd_spm_core_context_t;
| | ^
| services/std_svc/spmd/spmd_private.h:58:3: note: previous definition is here
| 58 | } spmd_spm_core_context_t;
| | ^
| CC services/std_svc/std_svc_setup.c
| 1 error generated.
| In file included from services/std_svc/spmd/spmd_main.c:35:
| services/std_svc/spmd/spmd_private.h:58:3: error: redefinition of typedef
| 'spmd_spm_core_context_t' is a C11 feature [-Werror,-Wtypedef-redefinition]
| 58 | } spmd_spm_core_context_t;
| | ^
| include/services/el3_spmd_logical_sp.h:15:38: note: previous definition is here
| 15 | typedef struct spmd_spm_core_context spmd_spm_core_context_t;
| | ^
| 1 error generated.

A structure 'spmd_spm_core_context_t' defined in 'spmd_private.h' is
also declared in 'el3_spmd_logical_sp.h' as it is used in a couple of
function declarations. These function declarations can be moved to
spmd_private.h as they are not needed elsewhere.

Change-Id: Ic6b9a277abe00cb7129f671570abf7255be62dfa
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>

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chore(tc): enable the full 16GB DRAM for TC3 and TC4 as default

Previously we only enabled 8GB unless we were loading the filesystem
from RAM.

Change-Id: Iae60ef460b8cf70f28e62a79db32405daf029e8a
S

chore(tc): enable the full 16GB DRAM for TC3 and TC4 as default

Previously we only enabled 8GB unless we were loading the filesystem
from RAM.

Change-Id: Iae60ef460b8cf70f28e62a79db32405daf029e8a
Signed-off-by: Ben Horgan <ben.horgan@arm.com>
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>

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Merge "feat(mt8196): initialize platform for MediaTek MT8196" into integration

feat(mt8196): initialize platform for MediaTek MT8196

- Add basic platform setup.
- Add MT8196 documentation at docs/plat/.
- Add generic CPU helper functions.
- Add basic register address.
- Add ti

feat(mt8196): initialize platform for MediaTek MT8196

- Add basic platform setup.
- Add MT8196 documentation at docs/plat/.
- Add generic CPU helper functions.
- Add basic register address.
- Add timer driver configuration.

Change-Id: I07fcdeb785fcda4a955c11c39a345da4ad05ef04
Signed-off-by: Gavin Liu <gavin.liu@mediatek.com>

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Merge changes from topic "rd1ae-bl32" into integration

* changes:
feat(rd1ae): add Generic Timer in device tree
docs(rd1ae): update documentation to include BL32
feat(rd1ae): add support for O

Merge changes from topic "rd1ae-bl32" into integration

* changes:
feat(rd1ae): add Generic Timer in device tree
docs(rd1ae): update documentation to include BL32
feat(rd1ae): add support for OP-TEE SPMC

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feat(rd1ae): add Generic Timer in device tree

Add a node for AP_REFCLK Non-Secure Generic Timer in device tree, which
acts as a system timer to fix the failure of SystemReady IR ACS BSA
test case 40

feat(rd1ae): add Generic Timer in device tree

Add a node for AP_REFCLK Non-Secure Generic Timer in device tree, which
acts as a system timer to fix the failure of SystemReady IR ACS BSA
test case 402.

Refer to https://github.com/ARM-software/bsa-acs/blob/v23.09_REL1.0.6\
/docs/arm_bsa_testcase_checklist.rst?plain=1#L115
for more information.

Signed-off-by: Ziad Elhanafy <ziad.elhanafy@arm.com>
Signed-off-by: David Hu <david.hu2@arm.com>
Change-Id: I3e63a5ecfd8c6211f917ca3844b8b7bda208d83a

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docs(rd1ae): update documentation to include BL32

Update the boot sequence in the RD-1 AE documentation
to include BL32 (OP-TEE).

Signed-off-by: Ziad Elhanafy <ziad.elhanafy@arm.com>
Change-Id: I25

docs(rd1ae): update documentation to include BL32

Update the boot sequence in the RD-1 AE documentation
to include BL32 (OP-TEE).

Signed-off-by: Ziad Elhanafy <ziad.elhanafy@arm.com>
Change-Id: I25fdc114bb71d3ad7e1bb2d845f758d6af037e3d

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Merge changes from topic "dtpm_poc" into integration

* changes:
refactor(rpi3): move mbedtls helper to common code
fix(rpi3): use correct name for include guards