Tegra210: Enable WDT_CPU interrupt for FIQ Debugger

This patch enables the watchdog timer's interrupt as an FIQ
interrupt to the CPU. The interrupt generated by the watchdog
is connected to the flow

Tegra210: Enable WDT_CPU interrupt for FIQ Debugger

This patch enables the watchdog timer's interrupt as an FIQ
interrupt to the CPU. The interrupt generated by the watchdog
is connected to the flow controller for power management reasons,
and needs to be routed to the GICD for it to reach the CPU.

Change-Id: I9437b516da2c5d763eca72694ed7f3c7389b3d9e
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: flowctrl: helper functions to assist with cluster power states

This patch adds helper functions to help platforms with cluster state entry
and exit decisions.

* tegra_fc_ccplex_pgexit_lock()

Tegra: flowctrl: helper functions to assist with cluster power states

This patch adds helper functions to help platforms with cluster state entry
and exit decisions.

* tegra_fc_ccplex_pgexit_lock(): lock CPU power ungate
* tegra_fc_ccplex_pgexit_unlock(): unlock CPU power ungate
* tegra_fc_is_ccx_allowed(): CCx state entry allowed on this CPU?

Change-Id: I6490d34bf380dc03ae203eb3028f61984f06931c
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: bpmp: remove bpmp init failed error print

This patch removes the error print displayed when bpmp init
fails. On platforms that do not load the bpmp firmware, this
print is seen on every clust

Tegra: bpmp: remove bpmp init failed error print

This patch removes the error print displayed when bpmp init
fails. On platforms that do not load the bpmp firmware, this
print is seen on every cluster idle and powerdown request,
cluttering the logs.

Change-Id: I9e30007a913080406052fc32d5360ff70a019d75
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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tlkd: support new TLK SMCs

This patch adds support to handle following TLK SMCs:
{TLK_SS_REGISTER_HANDLER, TLK_REGISTER_NS_DRAM_RANGES, TLK_SET_ROOT_OF_TRUST}

These SMCs need to be supported in ATF

tlkd: support new TLK SMCs

This patch adds support to handle following TLK SMCs:
{TLK_SS_REGISTER_HANDLER, TLK_REGISTER_NS_DRAM_RANGES, TLK_SET_ROOT_OF_TRUST}

These SMCs need to be supported in ATF in order to forward them to
TLK. Otherwise, these functionalities won't work.

Brief:
TLK_SS_REGISTER_HANDLER: This SMC is issued by TLK Linux Driver to
set up secure storage buffers.

TLK_REGISTER_NS_DRAM_RANGES: Cboot performs this SMC during boot to
pass NS memory ranges to TLK.

TLK_SET_ROOT_OF_TRUST: Cboot performs this SMC during boot to pass
Verified Boot parameters to TLK.

Change-Id: I18af35f6dd6f510dfc22c1d1d1d07f643c7b82bc
Reviewed-on: https://git-master.nvidia.com/r/1643851
Signed-off-by: Mihir Joshi <mihirj@nvidia.com>

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Tegra: fiq_glue: support to handle LEGACY_FIQ PPIs for Tegra SoCs

This patch adds support to handle secure PPIs for Tegra watchdog timers. This
functionality is currently protected by the ENABLE_WDT

Tegra: fiq_glue: support to handle LEGACY_FIQ PPIs for Tegra SoCs

This patch adds support to handle secure PPIs for Tegra watchdog timers. This
functionality is currently protected by the ENABLE_WDT_LEGACY_FIQ_HANDLING
configuration variable and is only enabled for Tegra210 platforms, for now.

Change-Id: I0752ef54a986c58305e1bc8ad9be71d4a8bbd394
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: flowctrl: support to enable/disable WDT's legacy FIQ routing

On earlier Tegra platforms, e.g. Tegra210, the watchdog timer's FIQ interrupt
is not direclty wired to the GICD. It goes to the fl

Tegra: flowctrl: support to enable/disable WDT's legacy FIQ routing

On earlier Tegra platforms, e.g. Tegra210, the watchdog timer's FIQ interrupt
is not direclty wired to the GICD. It goes to the flow controller instead, for
power state management. But the flow controller can route the FIQ to the GICD,
as a PPI, which can then get routed to the target CPU.

This patch adds routines to enable/disable routing the legacy FIQ used by
the watchdog timers, to the GICD.

Change-Id: Idd07c88c8d730b5f0e93e3a6e4fdc59bdcb2161b
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: SiP: set GPU in reset after vpr resize

Whenever the VPR memory is resized, the GPU is put into reset first
and then the new VPR parameters are programmed to the memory controller
block. There

Tegra: SiP: set GPU in reset after vpr resize

Whenever the VPR memory is resized, the GPU is put into reset first
and then the new VPR parameters are programmed to the memory controller
block. There exists a scenario, where the GPU might be out before we
program the new VPR parameters. This means, the GPU would still be
using older settings and leak secrets.

This patch puts the GPU back into reset, if it is out of reset after
resizing VPR, to mitigate this hole.

Change-Id: I38a1000e3803f80909efcb02e27da4bd46909931
Signed-off-by: Jeetesh Burman <jburman@nvidia.com>

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Tegra: handle FIQ interrupts when NS handler is not registered

This patch updates the secure interrupt handler to mark the interrupt
as complete in case the NS world has not registered a handler.

C

Tegra: handle FIQ interrupts when NS handler is not registered

This patch updates the secure interrupt handler to mark the interrupt
as complete in case the NS world has not registered a handler.

Change-Id: Iebe952305f7db46375303699b6150611439475df
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: bpmp_ipc: support to enable/disable module clocks

This patch adds support to the bpmp_ipc driver to allow clients to
enable/disable clocks to hardware blocks. Currently, the API only
supports

Tegra: bpmp_ipc: support to enable/disable module clocks

This patch adds support to the bpmp_ipc driver to allow clients to
enable/disable clocks to hardware blocks. Currently, the API only
supports SE devices.

Change-Id: I9a361e380c0bcda59f5a92ca51c86a46555b2e90
Signed-off-by: steven kao <skao@nvidia.com>

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Tegra: fix offset used to dump GICD registers from crash handler

The GICD registers are 32-bits wide whereas the crash handler was reading
them as 64-bit ones. This patch fixes the code to read the

Tegra: fix offset used to dump GICD registers from crash handler

The GICD registers are 32-bits wide whereas the crash handler was reading
them as 64-bit ones. This patch fixes the code to read the GICD registers,
32-bits at a time, from the paltform's crash handler.

Change-Id: If3d6608529684ecc02be6a1b715012310813b2a4
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: default platform handler for the CPU_STANDBY state

This patch adds a default implementation for the platform specific
CPU standby power handler. Tegra SoCs can override this handler
with thei

Tegra: default platform handler for the CPU_STANDBY state

This patch adds a default implementation for the platform specific
CPU standby power handler. Tegra SoCs can override this handler
with their own implementations.

Change-Id: I91e513842f194b1e2b1defa2d833bb4d9df5f06b
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra186: smmu: add support for backup multiple smmu regs

Modifying smmu macros to pass base address of smmu so that it can be
used with multiple smmus.

Added macro for combining smmu backup regs t

Tegra186: smmu: add support for backup multiple smmu regs

Modifying smmu macros to pass base address of smmu so that it can be
used with multiple smmus.

Added macro for combining smmu backup regs that can be used for multiple
smmus.

Change-Id: I4f3bb83d66d5df14a3b91bc82f7fc26ec8e4592e
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>

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User Guide: Move ARM_PLAT_MT doc to Arm build flags

ARM_PLAT_MT build flag is specific to Arm platforms so should not
be classified as a common build option.

Change-Id: I79e411958846759a5b60d770e53

User Guide: Move ARM_PLAT_MT doc to Arm build flags

ARM_PLAT_MT build flag is specific to Arm platforms so should not
be classified as a common build option.

Change-Id: I79e411958846759a5b60d770e53f44bbec5febe6
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

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Remove dead code related to LOAD_IMAGE_V2=0

Commit ed51b51f7a9163a ("Remove build option LOAD_IMAGE_V2") intended
to remove all code related to LOAD_IMAGE_V2=0 but missed a few things.

Change-Id: I

Remove dead code related to LOAD_IMAGE_V2=0

Commit ed51b51f7a9163a ("Remove build option LOAD_IMAGE_V2") intended
to remove all code related to LOAD_IMAGE_V2=0 but missed a few things.

Change-Id: I16aaf52779dd4af1e134e682731328c5f1e5d622
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

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hikey960: EDMAC: leave channel 0 as secure

Channel 0 is used to communicate with LPM3, a coprocessor
for power management. Leave it as secure.

Signed-off-by: Ryan Grachek <ryan@edited.us>

Merge pull request #1798 from pbeesley-arm/pb/fix-code-style

doc: Fix broken code blocks in coding guidelines

doc: Fix broken code blocks in coding guidelines

Sections 2.2, 2.3 and 2.4 contained example code blocks that were not
being formatted properly due to missing newlines.

Change-Id: I0dbce90c931cf69e

doc: Fix broken code blocks in coding guidelines

Sections 2.2, 2.3 and 2.4 contained example code blocks that were not
being formatted properly due to missing newlines.

Change-Id: I0dbce90c931cf69e4f47d2ccbcc8bc0e20f8fd66
Signed-off-by: Paul Beesley <paul.beesley@arm.com>

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Merge pull request #1797 from antonio-nino-diaz-arm/an/remove-smccc-v2

Remove support for the SMC Calling Convention 2.0

Merge pull request #1745 from svenauhagen/bugfix/a8k

Armada8k GPIO Register macro fix

Merge pull request #1793 from marex/arm/master/fixes-v2.0.0

Arm/master/fixes v2.0.0

Merge pull request #1792 from satheesbalya-arm/sb1/sb1_2159_v84_xlat

lib/xlat_tables: Add support for ARMv8.4-TTST

Merge pull request #1795 from pbeesley-arm/pb/code-style

Move coding guidelines into docs directory

Merge pull request #1753 from Yann-lms/emmc_ret

mmc: correctly check ret in mmc_fill_device_info

Remove support for the SMC Calling Convention 2.0

This reverts commit 2f370465241c ("Add support for the SMC Calling
Convention 2.0").

SMCCC v2.0 is no longer required for SPM, and won't be needed

Remove support for the SMC Calling Convention 2.0

This reverts commit 2f370465241c ("Add support for the SMC Calling
Convention 2.0").

SMCCC v2.0 is no longer required for SPM, and won't be needed in the
future. Removing it makes the SMC handling code less complicated.

The SPM implementation based on SPCI and SPRT was using it, but it has
been adapted to SMCCC v1.0.

Change-Id: I36795b91857b2b9c00437cfbfed04b3c1627f578
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

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lib/xlat_tables: Add support for ARMv8.4-TTST

ARMv8.4-TTST (Small Translation tables) relaxes the lower limit on the
size of translation tables by increasing the maximum permitted value
of the T1SZ

lib/xlat_tables: Add support for ARMv8.4-TTST

ARMv8.4-TTST (Small Translation tables) relaxes the lower limit on the
size of translation tables by increasing the maximum permitted value
of the T1SZ and T0SZ fields in TCR_EL1, TCR_EL2, TCR_EL3, VTCR_EL2 and
VSTCR_EL2.

This feature is supported in AArch64 state only.

This patch adds support for this feature to both versions of the
translation tables library. It also removes the static build time
checks for virtual address space size checks to runtime assertions.

Change-Id: I4e8cebc197ec1c2092dc7d307486616786e6c093
Signed-off-by: Sathees Balya <sathees.balya@arm.com>

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