fix(cpus): workaround for Cortex-A725 erratum 2874943

Cortex-A725 erratum 2874943 is a Cat B erratum that applies
to revision r0p0 when FEAT_SPE is enabled, it is fixed in r0p1.

This erratum can be

fix(cpus): workaround for Cortex-A725 erratum 2874943

Cortex-A725 erratum 2874943 is a Cat B erratum that applies
to revision r0p0 when FEAT_SPE is enabled, it is fixed in r0p1.

This erratum can be avoided by setting bits[58:57] to 0b11 in CPUACTLR_EL1.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-2832921/latest/

Change-Id: I686bbde8756d52afee92097ec05b97138b550025
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Cortex-A65 erratum 1227419

Cortex-A65 erratum 1227419 is a Cat B erratum that applies
to r0p0, r1p0, it is fixed in r1p1.

This erratum can be avoided by setting CPUACTLR_E

fix(cpus): workaround for Cortex-A65 erratum 1227419

Cortex-A65 erratum 1227419 is a Cat B erratum that applies
to r0p0, r1p0, it is fixed in r1p1.

This erratum can be avoided by setting CPUACTLR_EL1[51] to 1.
This bit disables the cross-thread sharing in instruction uTLB.

SDEN documentation:
https://developer.arm.com/documentation/SDEN1065159/latest/

Change-Id: I42371e7d53fce3a7e085bf0b348f080fa323fb51
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Cortex-A65 erratum 1179935

Cortex-A65 erratum 1179935 is a Cat B erratum that applies
to r0p0, it is fixed in r1p0.

This erratum can be avoided by setting CPUACTLR_EL1[49]

fix(cpus): workaround for Cortex-A65 erratum 1179935

Cortex-A65 erratum 1179935 is a Cat B erratum that applies
to r0p0, it is fixed in r1p0.

This erratum can be avoided by setting CPUACTLR_EL1[49] to 1. The bit
prevents translation table walks from allocating lines into the
L1 cache. This has a negligible impact on performance when an
L2 cache is present.

SDEN documentation:
https://developer.arm.com/documentation/SDEN1065159/latest/

Change-Id: Ie59a4897f849269a590d8fa2d25cceab5f2cba3c
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Cortex-A76AE erratum 2371140

Cortex-A76AE erratum 2371140 is a Cat B erratum that applies
to all revisions <= r1p1, and is still open.

This erratum can be avoided by setti

fix(cpus): workaround for Cortex-A76AE erratum 2371140

Cortex-A76AE erratum 2371140 is a Cat B erratum that applies
to all revisions <= r1p1, and is still open.

This erratum can be avoided by setting CPUACTLR2_EL1[0] to 1. The
bit force PLDW/PFRM ST to behave like PLD/PRFM LD and not cause
invalidations to other PE caches. There might be a small performance
degradation to this workaround for certain workloads that share data.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1277541/1700/?lang=en

Change-Id: Id65846bebde1a0911ba11956202d0d255d3c8c82
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Cortex-A76AE erratum 1969401

Cortex-A76AE erratum 1969401 is a Cat B erratum that applies
to r0p0 and r1p0, it is fixed in r1p1.

This erratum can be avoided by inserting a

fix(cpus): workaround for Cortex-A76AE erratum 1969401

Cortex-A76AE erratum 1969401 is a Cat B erratum that applies
to r0p0 and r1p0, it is fixed in r1p1.

This erratum can be avoided by inserting a DMB ST before acquire
atomic instructions without release semantics.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1277541/1700/?lang=en

Change-Id: I893452450d430833e6c5a8e33a1e37b708218576
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Cortex-A76AE erratum 1931435

Cortex-A76AE erratum 1931435 is a Cat B erratum that applies
to r0p0 and r1p0, it is fixed in r1p1.

This erratum can be avoided by setting CPU

fix(cpus): workaround for Cortex-A76AE erratum 1931435

Cortex-A76AE erratum 1931435 is a Cat B erratum that applies
to r0p0 and r1p0, it is fixed in r1p1.

This erratum can be avoided by setting CPUACTLR_EL1[13] to 1. This bit
delays instruction fetch after branch misprediction. This workaround
will have a small impact on performance.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1277541/1700/?lang=en

Change-Id: I1baba8752f5f2e2ab5c873030e1f00cbb8cf1e60
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Cortex-A76AE erratum 1931427

Cortex-A76AE erratum 1931427 is a Cat B erratum that applies
to r0p0 and r1p0, it is fixed in r1p1.

This erratum can be avoided by setting CPU

fix(cpus): workaround for Cortex-A76AE erratum 1931427

Cortex-A76AE erratum 1931427 is a Cat B erratum that applies
to r0p0 and r1p0, it is fixed in r1p1.

This erratum can be avoided by setting CPUACTLR2_EL1[2] to 1. The bit
to force Atomic Store operations to write-back memory to be performed
in the L1 data cache.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1277541/1700/?lang=en

Change-Id: I31566838f894372e5627abda8b0bea1505f11f5d
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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Merge "feat(imx8m): keep console at runtime when building TF-A/bl31 with DEBUG" into integration

Merge changes from topic "image_decryption" into integration

* changes:
feat(fvp): extend image decryption support for FVP
fix(io): add NULL check for spec io_open FIP

Merge "fix(tc): correct register write in rng trap handler" into integration

Merge "fix(rcar5): enable missing FEAT_AMUv1p1 on R-Car Gen5 to fix the build" into integration

fix(rcar5): enable missing FEAT_AMUv1p1 on R-Car Gen5 to fix the build

Since commit 6edbd2d6a8ae ("fix(cpufeat): require FEAT_AMUv1p1 to
enable the auxiliary counters") the ENABLE_AMU_AUXILIARY_COUN

fix(rcar5): enable missing FEAT_AMUv1p1 on R-Car Gen5 to fix the build

Since commit 6edbd2d6a8ae ("fix(cpufeat): require FEAT_AMUv1p1 to
enable the auxiliary counters") the ENABLE_AMU_AUXILIARY_COUNTERS
requires ENABLE_FEAT_AMUv1p1 to be enabled as well. Enable missing
ENABLE_FEAT_AMUv1p1 to fix the build, which was broken because the
R-Car Gen5 and FEAT_AMUv1p1 commits landed in reverse order.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Change-Id: I834aff7798d7a5e10014fbd9f1ac8a97908b9aab

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Merge "feat(rcar): add initial BL31 support for Renesas R-Car X5H" into integration

Merge "fix(intel): allow kernel access to TSN TBU stream control registers" into integration

Merge "fix: remove circular dependency on ENABLE_FEAT_RAS" into integration

feat(clk): add get_possible_parents_num callback

This callback will be used to get number of possible parents if
the underlying clock driver supports this option.

Change-Id: I9459c878dd2155ff24b72c

feat(clk): add get_possible_parents_num callback

This callback will be used to get number of possible parents if
the underlying clock driver supports this option.

Change-Id: I9459c878dd2155ff24b72cef6851180e105be432
Signed-off-by: Kamlesh Gurudasani <kamlesh@ti.com>

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Merge "fix(libfdt): fix coverity reported issue" into integration

Merge changes from topic "gr/cov_fixes" into integration

* changes:
fix(libc): fix coverity deadcode issue
fix(zlib): fix overflow issue from coverity

Merge changes from topic "tc-lsc-25-cpu-libs" into integration

* changes:
feat(cpus): add support for LSC25 E-core CPU
feat(cpus): add support for LSC25 P-core CPU

Merge "feat(crypto): enable SIMD crypto extensions for S-EL1" into integration

feat(cpufeat): add support for FEAT_UINJ

FEAT_UINJ allows higher ELs to inject Undefined Instruction exceptions
into lower ELs by setting SPSR_ELx.UINJ, which updates PSTATE.UINJ on
exception return

feat(cpufeat): add support for FEAT_UINJ

FEAT_UINJ allows higher ELs to inject Undefined Instruction exceptions
into lower ELs by setting SPSR_ELx.UINJ, which updates PSTATE.UINJ on
exception return. When PSTATE.UINJ is set, instruction execution at the
lower EL raises an Undefined Instruction exception (EC=0b000000).

This patch introduces support for FEAT_UINJ by updating the
inject_undef64() to use hardware undef injection if supported.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I48ad56a58eaab7859d508cfa8dfe81130b873b6b

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feat(cpufeat): enable mandatory Armv9.4–Armv9.6 features by default

This patch sets Armv9.4-Armv9.6 mandatory features
to 1 by default.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>

feat(cpufeat): enable mandatory Armv9.4–Armv9.6 features by default

This patch sets Armv9.4-Armv9.6 mandatory features
to 1 by default.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I12382e8765f3af7a5428abb1cf1ea0407fdd3849

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fix(cpufeat): update feature names and comments

Fix supported feature list for FEAT_CSV2_2/CSV2_3 and add clearer
descriptions for LS64_ACCDATA, AIE, and PFAR features.

Signed-off-by: Arvind Ram Pr

fix(cpufeat): update feature names and comments

Fix supported feature list for FEAT_CSV2_2/CSV2_3 and add clearer
descriptions for LS64_ACCDATA, AIE, and PFAR features.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I0073db4007b90e4a37c337af789a7f5c98677372

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fix(cpufeat): simplify AArch32 feature disablement

Remove redundant conditional checks for unsupported features
(SPE, SVE, MPAM) in aarch32 builds and set them unconditionally
to 0. Add correspondin

fix(cpufeat): simplify AArch32 feature disablement

Remove redundant conditional checks for unsupported features
(SPE, SVE, MPAM) in aarch32 builds and set them unconditionally
to 0. Add corresponding constraint checks to ensure these
features are not enabled when ARCH=aarch32.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I6486b54c69bf0c273371235d1661fafbcb7abb8c

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Merge "fix(gpt): remove unused `gpt_disable` function" into integration