Merge "fix(rcar3): disable stack protector for functions in SRAM" into integration

feat(cpufeat): add the newly analyzed features to FEATURE_DETECTION

Now that the 2024 features have been analysed, bump those that don't
need any specific EL3 support so that FEATURE_DETECTION doesn

feat(cpufeat): add the newly analyzed features to FEATURE_DETECTION

Now that the 2024 features have been analysed, bump those that don't
need any specific EL3 support so that FEATURE_DETECTION doesn't complain
when it encounters them.

Change-Id: I3a2243d021a9a5385d14b3c1d569142e34145e51
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

show more ...

docs(cpufeat): add analysis of 2024 features

Having gone through the list, write down the features that require no
EL3 enablement and leave out the ones that do.

Minor revisions of major features (

docs(cpufeat): add analysis of 2024 features

Having gone through the list, write down the features that require no
EL3 enablement and leave out the ones that do.

Minor revisions of major features (eg FEAT_SPE) that introduce a
mandatory feature are counted as independent features.

Change-Id: Ifeb88c8fb7a754eaa0df2edaa935090cbdfa35ad
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

show more ...

fix(cpufeat): add FEAT_SPE to FEATURE_DETECTION

Documentation in docs/architecture_features.rst suggests we're okay with
anything up to FEAT_SPEv1p3 but FEAT_DETECT is unaware of it. Add it to
the l

fix(cpufeat): add FEAT_SPE to FEATURE_DETECTION

Documentation in docs/architecture_features.rst suggests we're okay with
anything up to FEAT_SPEv1p3 but FEAT_DETECT is unaware of it. Add it to
the list.

Change-Id: I8ac773361fb8d18b850da1e45fdb6a54cfe65063
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

show more ...

Merge "fix(debug): add debug log build option" into integration

Merge "fix(morello): avoid capability tag fault on data access" into integration

Merge changes from topic "morello_upstream" into integration

* changes:
feat(morello): add capability load/store/track support to MMU
feat(morello): add Morello capability enablement changes

Merge "fix(docs): update sme disconnect on power down" into integration

fix(debug): add debug log build option

When log level set to verbose, xlat prints
alot of translation table debug logs.These
detail logs keeps on printing for minutes
and increase boot time. Also, n

fix(debug): add debug log build option

When log level set to verbose, xlat prints
alot of translation table debug logs.These
detail logs keeps on printing for minutes
and increase boot time. Also, not all users
might be interested in the xlat detail
logs when verbose is on.

LOG_DEBUG is added to print xlat detail
logs only when someone intentionally
enables logging.

Change-Id: I3308b49779a692bdce87fb6929c88fdcb713e628
Signed-off-by: Jaiprakash Singh <jaiprakashs@marvell.com>

show more ...

fix(rcar3): disable stack protector for functions in SRAM

Disable the BL31 stack protector for all functions placed in SRAM,
because the canary value in __stack_chk_guard in DRAM can not be
read whe

fix(rcar3): disable stack protector for functions in SRAM

Disable the BL31 stack protector for all functions placed in SRAM,
because the canary value in __stack_chk_guard in DRAM can not be
read when running Suspend To RAM code from SRAM. The SSP functions
in DRAM can also not be called from that code. Make sure the code
in SRAM is self-contained by marking rcar_pwrc_go_suspend_to_ram()
as noinline. To assure the stack protector is active otherwise,
use no_stack_protector function attribute for the select functions
which are placed in SRAM.

Change-Id: Idc43e70fd5217ea130a48c46f227a37c568dc8bd
Fixes: cfa466ab733f ("feat(rcar3): enable the stack protection")
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Signed-off-by: Dien Pham <dien.pham.ry@renesas.com>
Signed-off-by: Hieu Nguyen <hieu.nguyen.dn@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>

show more ...

fix(morello): avoid capability tag fault on data access

TF-A runtime service at EL3 switches the stack pointer from SP_EL3
to SP_EL0. This creates a capability tag fault when the DDC_EL0 is
zeroed o

fix(morello): avoid capability tag fault on data access

TF-A runtime service at EL3 switches the stack pointer from SP_EL3
to SP_EL0. This creates a capability tag fault when the DDC_EL0 is
zeroed out (purecap user space) as any data accesses computes
tag/permission with DDC_EL0 value when SpSel is 0 and when EL3 is
in hybrid mode.

As a workaround, this patch creates a per cpu context variable
to store DDC_EL0 value so that when EL3 runtime is entered DDC_EL0
is saved on to stack. DDC_EL3 is then copied into DDC_EL0 after
switching SP to SP_EL0. Once the runtime finishes, during el3_exit,
the saved DDC_EL0 is restored from stack.

Signed-off-by: Selvarasu Ganesan <selvarasu.ganesan@arm.com>
Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>
Signed-off-by: Varshit Pandya <varshit.pandya@arm.com>
Change-Id: I4e4010f0e20913cb4e35b58fb49a177bdf26feb1

show more ...

feat(morello): add capability load/store/track support to MMU

Morello architecture adds additional bits to TCR_EL3 and uses the
HWU bits of page/block descriptors to provision permission for
loading

feat(morello): add capability load/store/track support to MMU

Morello architecture adds additional bits to TCR_EL3 and uses the
HWU bits of page/block descriptors to provision permission for
loading, storing and tracking of valid capability tags.

This patch reserves bit 31 of the existing translation table
attribute field which can be used by the user to enable capability
load/store/track permission for a given memory region.

This patch also enables this permission for BL31 region.

Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>
Signed-off-by: Varshit Pandya <varshit.pandya@arm.com>
Change-Id: I1939c70aac3585969d74b0956529681e840d6f63

show more ...

feat(morello): add Morello capability enablement changes

This patch adds a build macro ENABLE_FEAT_MORELLO which when set will
compile BL31 firmware with changes required to boot capability
aware so

feat(morello): add Morello capability enablement changes

This patch adds a build macro ENABLE_FEAT_MORELLO which when set will
compile BL31 firmware with changes required to boot capability
aware software.

It also adds helper function in c and assmbly to check if morello
hardware is present and if morello capability is enabled or not.

CE field, bits [23:20] in ID_AA64PFR1_EL1 defines whether morello
architecture is present or not, 0b0000 indicates that it is absent
and 0b0001 indicates that it is present. While whether capabilities
are enabled or not is decided at runtime with ENABLE_FEAT_MORELLO build
option.

Reference: https://developer.arm.com/documentation/ddi0606/latest/

Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>
Signed-off-by: Varshit Pandya <varshit.pandya@arm.com>
Change-Id: Ib16877acbfcb72c4bd8c08e97e44edc0a3e46089

show more ...

fix(cpufeat): enable access to extended BRPs/WRPs

Access to Extended Breakpoints(BRPs) and Watchpoints(WRPs) are enabled
through EBWE bit and this available from DebugV8P9. So enable access to
mode

fix(cpufeat): enable access to extended BRPs/WRPs

Access to Extended Breakpoints(BRPs) and Watchpoints(WRPs) are enabled
through EBWE bit and this available from DebugV8P9. So enable access to
mode select register default from lower EL's.

Though this bit RES0 when we have less than 16 BRPs/WRPs the Mode select
register is also RAZ/WI. So having EBWE write by default is harmless.
And will avoid trap to EL3 when enable access to bank selection when we
have more than 16 BRPs/WRPs.

Change-Id: Ib308be758c0beedde05a5558b0d24a161b79273a
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

show more ...

fix(docs): update sme disconnect on power down

With `ERRATA_SME_POWER_DOWN` enabled we disconnect SME from
core to power down the core correctly, we actually don't disable sme.

Change-Id: I42b99bd5

fix(docs): update sme disconnect on power down

With `ERRATA_SME_POWER_DOWN` enabled we disconnect SME from
core to power down the core correctly, we actually don't disable sme.

Change-Id: I42b99bd5ef125868f55a2a3ef96c0ac1b054f509
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

show more ...

Merge changes from topic "bk/amu_private" into integration

* changes:
fix(cpufeat): prevent FEAT_AMU counters 2 and 3 from counting across worlds
fix(cpufeat): disable FEAT_AMU counters on conte

Merge changes from topic "bk/amu_private" into integration

* changes:
fix(cpufeat): prevent FEAT_AMU counters 2 and 3 from counting across worlds
fix(cpufeat): disable FEAT_AMU counters on context restore
feat(per-cpu): migrate AArch32 amu_ctx to per-cpu framework

show more ...

Merge "fix(cpus): enable Neoverse-V2 external LLC support" into integration

fix(cpus): enable Neoverse-V2 external LLC support

Change-Id: I9582c7405db6862e77db240822e241d4082966f2
Signed-off-by: Jaiprakash Singh <jaiprakashs@marvell.com>

Merge changes Ia7a1c37b,Ia933c505 into integration

* changes:
feat(rcar): fold console_rcar_* functions into rcar_printf.c
feat(rcar): rewrite SCIF driver from assembler to C

feat(rcar): fold console_rcar_* functions into rcar_printf.c

The three console_rcar_{init,putc,flush}() no-op functions can
easily be C functions, they do not need assembler wrappers. Move
the funct

feat(rcar): fold console_rcar_* functions into rcar_printf.c

The three console_rcar_{init,putc,flush}() no-op functions can
easily be C functions, they do not need assembler wrappers. Move
the functions into rcar_printf.c which is part of the custom
R-Car Gen3 memory logging console. Remove rcar_printf.c from
BL2 builds, as it is not useful there. Rename rcar_set_log_data()
to console_rcar_putc() and update its signature, it is no longer
necessary to have such a wrapper around C function.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Change-Id: Ia7a1c37b2151f6217cde70ffd2b367643d3184e4

show more ...

feat(rcar): rewrite SCIF driver from assembler to C

Rewrite the SCIF driver from difficult to read assembler to plain C.
Use scif-common.c which contains putc() and flush() helper functions
to avoid

feat(rcar): rewrite SCIF driver from assembler to C

Rewrite the SCIF driver from difficult to read assembler to plain C.
Use scif-common.c which contains putc() and flush() helper functions
to avoid duplication, so only fill in the initialization code. Drop
support for external clock, which is unused. Clean up macros and drop
ones which are not referenced.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Change-Id: Ia933c505c33e133e45448c82776a17629f3df1eb

show more ...

Merge "fix(rdaspen): dts: make cache nodes DT spec compliant" into integration

refactor(aarch64): remove crash reporting's dependency on cpu_data

Crash reporting is useful as early as possible, even before most of the
runtime has been set up. This means that all of its depende

refactor(aarch64): remove crash reporting's dependency on cpu_data

Crash reporting is useful as early as possible, even before most of the
runtime has been set up. This means that all of its dependencies,
currently only cpu_data, must be set up as early as possible too. This
can be constraining as fiddling with the general EL3 runtime from the
early entrypoint is very difficult. So remove the cpu_data dependency.
Further benefits are that crash reporting will work even earlier (during
cpu reset functions!) and also in other BLs.

Change-Id: I92bb6b3921c6dec10560f8341b3bca5cdacfb492
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

show more ...

fix(el3-runtime): remove lower_el_panic()

A panic at EL3 is bad news and should never happen. What caused it isn't
exactly relevant or possible to figure out without manual debugging
(surely there w

fix(el3-runtime): remove lower_el_panic()

A panic at EL3 is bad news and should never happen. What caused it isn't
exactly relevant or possible to figure out without manual debugging
(surely there wouldn't have been a panic if not). A misbehaving lower EL
should never be able to cause problems for a higher EL and since EL3 is
in control of all lower ELs a panic at EL3 means that there is a
problem with EL3.

This patch removes lower_el panic and replaces it with a simple panic
for simplicity. There is a slight loss of information when an AArch32
lower EL has one of its instructions trapped by EL3. An explicit error
message is added to preserve this information.

Change-Id: Iefd20eb43d69cbcf6d66ed5cc894c4e0255782e3
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

show more ...

Merge changes from topic "xlnx_fix_misra_opteed" into integration

* changes:
fix(optee): initialize the structure
fix(optee): add missing curly braces
fix(optee): add parenthesis for macro exp

Merge changes from topic "xlnx_fix_misra_opteed" into integration

* changes:
fix(optee): initialize the structure
fix(optee): add missing curly braces
fix(optee): add parenthesis for macro expressions
fix(optee): move function to conditional block
fix(optee): add boolean type for expressions
fix(optee): evaluate condition for boolean
fix(optee): typecast operands to match data type
fix(el3-runtime): resolve essential-type mismatch

show more ...