1/* 2 * Copyright (c) 2015-2026, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#ifndef EL3_COMMON_MACROS_S 8#define EL3_COMMON_MACROS_S 9 10#include <arch.h> 11#include <asm_macros.S> 12#include <assert_macros.S> 13#include <context.h> 14#include <lib/el3_runtime/cpu_data.h> 15#include <lib/per_cpu/per_cpu_macros.S> 16 17 /* 18 * Helper macro to initialise EL3 registers we care about. 19 */ 20 .macro el3_arch_init_common 21 /* --------------------------------------------------------------------- 22 * SCTLR_EL3 has already been initialised - read current value before 23 * modifying. 24 * 25 * SCTLR_EL3.I: Enable the instruction cache. 26 * 27 * SCTLR_EL3.SA: Enable Stack Alignment check. A SP alignment fault 28 * exception is generated if a load or store instruction executed at 29 * EL3 uses the SP as the base address and the SP is not aligned to a 30 * 16-byte boundary. 31 * 32 * SCTLR_EL3.A: Enable Alignment fault checking. All instructions that 33 * load or store one or more registers have an alignment check that the 34 * address being accessed is aligned to the size of the data element(s) 35 * being accessed. 36 * 37 * SCTLR_EL3.BT: PAuth instructions are compatible with bti jc 38 * --------------------------------------------------------------------- 39 */ 40 mov_imm x1, (SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT) 41 mrs x0, sctlr_el3 42#if ENABLE_BTI 43 bic x0, x0, #SCTLR_BT_BIT 44#endif 45 orr x0, x0, x1 46 msr sctlr_el3, x0 47 isb 48 49#if ENABLE_FEAT_SCTLR2 50#if ENABLE_FEAT_SCTLR2 > 1 51 is_feat_sctlr2_present_asm x1 52 beq feat_sctlr2_not_supported\@ 53#endif 54 mov x1, #SCTLR2_RESET_VAL 55 msr SCTLR2_EL3, x1 56feat_sctlr2_not_supported\@: 57#endif 58 59#ifdef IMAGE_BL31 60 /* --------------------------------------------------------------------- 61 * Initialise the per-cpu cache pointer to the CPU. 62 * --------------------------------------------------------------------- 63 */ 64 per_cpu_init 65#endif /* IMAGE_BL31 */ 66 67 /* --------------------------------------------------------------------- 68 * Initialise SCR_EL3, setting all fields rather than relying on hw. 69 * All fields are architecturally UNKNOWN on reset. The following fields 70 * do not change during the TF lifetime. The remaining fields are set to 71 * zero here but are updated ahead of transitioning to a lower EL in the 72 * function cm_init_context_common(). 73 * 74 * SCR_EL3.EEL2: Set to one if S-EL2 is present and enabled. 75 * 76 * NOTE: Modifying EEL2 bit along with EA bit ensures that we mitigate 77 * against ERRATA_V2_3099206. 78 * --------------------------------------------------------------------- 79 */ 80 mov_imm x0, SCR_RESET_VAL 81#if IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2 82 mrs x1, id_aa64pfr0_el1 83 and x1, x1, #(ID_AA64PFR0_SEL2_MASK << ID_AA64PFR0_SEL2_SHIFT) 84 cbz x1, 1f 85 orr x0, x0, #SCR_EEL2_BIT 86#endif 871: 88 msr scr_el3, x0 89 90 /* --------------------------------------------------------------------- 91 * Initialise MDCR_EL3, setting all fields rather than relying on hw. 92 * Some fields are architecturally UNKNOWN on reset. 93 */ 94 mov_imm x0, MDCR_EL3_RESET_VAL 95 msr mdcr_el3, x0 96 97 /* --------------------------------------------------------------------- 98 * Initialise CPTR_EL3, setting all fields rather than relying on hw. 99 * All fields are architecturally UNKNOWN on reset. 100 * --------------------------------------------------------------------- 101 */ 102 mov_imm x0, CPTR_EL3_RESET_VAL 103 msr cptr_el3, x0 104 105 .endm 106 107/* ----------------------------------------------------------------------------- 108 * This is the super set of actions that need to be performed during a cold boot 109 * or a warm boot in EL3. This code is shared by BL1 and BL31. 110 * 111 * This macro will always perform reset handling, architectural initialisations 112 * and stack setup. The rest of the actions are optional because they might not 113 * be needed, depending on the context in which this macro is called. This is 114 * why this macro is parameterised ; each parameter allows to enable/disable 115 * some actions. 116 * 117 * _init_sctlr: 118 * Whether the macro needs to initialise SCTLR_EL3, including configuring 119 * the endianness of data accesses. 120 * 121 * _warm_boot_mailbox: 122 * Whether the macro needs to detect the type of boot (cold/warm). The 123 * detection is based on the platform entrypoint address : if it is zero 124 * then it is a cold boot, otherwise it is a warm boot. In the latter case, 125 * this macro jumps on the platform entrypoint address. 126 * 127 * _secondary_cold_boot: 128 * Whether the macro needs to identify the CPU that is calling it: primary 129 * CPU or secondary CPU. The primary CPU will be allowed to carry on with 130 * the platform initialisations, while the secondaries will be put in a 131 * platform-specific state in the meantime. 132 * 133 * If the caller knows this macro will only be called by the primary CPU 134 * then this parameter can be defined to 0 to skip this step. 135 * 136 * _init_memory: 137 * Whether the macro needs to initialise the memory. 138 * 139 * _init_c_runtime: 140 * Whether the macro needs to initialise the C runtime environment. 141 * 142 * _exception_vectors: 143 * Address of the exception vectors to program in the VBAR_EL3 register. 144 * 145 * _pie_fixup_size: 146 * Size of memory region to fixup Global Descriptor Table (GDT). 147 * 148 * A non-zero value is expected when firmware needs GDT to be fixed-up. 149 * 150 * ----------------------------------------------------------------------------- 151 */ 152 .macro el3_entrypoint_common \ 153 _init_sctlr, _warm_boot_mailbox, _secondary_cold_boot, \ 154 _init_memory, _init_c_runtime, _exception_vectors, \ 155 _pie_fixup_size 156 157 .if \_init_sctlr 158 /* ------------------------------------------------------------- 159 * This is the initialisation of SCTLR_EL3 and so must ensure 160 * that all fields are explicitly set rather than relying on hw. 161 * Some fields reset to an IMPLEMENTATION DEFINED value and 162 * others are architecturally UNKNOWN on reset. 163 * 164 * SCTLR.EE: Set the CPU endianness before doing anything that 165 * might involve memory reads or writes. Set to zero to select 166 * Little Endian. 167 * 168 * SCTLR_EL3.WXN: For the EL3 translation regime, this field can 169 * force all memory regions that are writeable to be treated as 170 * XN (Execute-never). Set to zero so that this control has no 171 * effect on memory access permissions. 172 * 173 * SCTLR_EL3.SA: Set to zero to disable Stack Alignment check. 174 * 175 * SCTLR_EL3.A: Set to zero to disable Alignment fault checking. 176 * 177 * SCTLR.DSSBS: Set to zero to disable speculation store bypass 178 * safe behaviour upon exception entry to EL3. 179 * ------------------------------------------------------------- 180 */ 181 mov_imm x0, (SCTLR_RESET_VAL & ~(SCTLR_EE_BIT | SCTLR_WXN_BIT \ 182 | SCTLR_SA_BIT | SCTLR_A_BIT | SCTLR_DSSBS_BIT)) 183#if ENABLE_FEAT_RAS 184 /* If FEAT_RAS is present assume FEAT_IESB is also present */ 185 orr x0, x0, #SCTLR_IESB_BIT 186#endif 187 msr sctlr_el3, x0 188 isb 189 .endif /* _init_sctlr */ 190 191 .if \_warm_boot_mailbox 192 /* ------------------------------------------------------------- 193 * This code will be executed for both warm and cold resets. 194 * Now is the time to distinguish between the two. 195 * Query the platform entrypoint address and if it is not zero 196 * then it means it is a warm boot so jump to this address. 197 * ------------------------------------------------------------- 198 */ 199 bl plat_get_my_entrypoint 200 cbz x0, do_cold_boot 201 br x0 202 203 do_cold_boot: 204 .endif /* _warm_boot_mailbox */ 205 206 .if \_pie_fixup_size 207#if ENABLE_PIE 208 /* 209 * ------------------------------------------------------------ 210 * If PIE is enabled fixup the Global descriptor Table only 211 * once during primary core cold boot path. 212 * 213 * Compile time base address, required for fixup, is calculated 214 * using "pie_fixup" label present within first page. 215 * ------------------------------------------------------------ 216 */ 217 pie_fixup: 218 ldr x0, =pie_fixup 219 and x0, x0, #~(PAGE_SIZE_MASK) 220 mov_imm x1, \_pie_fixup_size 221 add x1, x1, x0 222 bl fixup_gdt_reloc 223#endif /* ENABLE_PIE */ 224 .endif /* _pie_fixup_size */ 225 226 /* --------------------------------------------------------------------- 227 * Set the exception vectors. 228 * --------------------------------------------------------------------- 229 */ 230 adr x0, \_exception_vectors 231 msr vbar_el3, x0 232 isb 233 234 call_reset_handler 235 236 el3_arch_init_common 237 238 /* --------------------------------------------------------------------- 239 * Set the el3 execution context(i.e. root_context). 240 * --------------------------------------------------------------------- 241 */ 242 setup_el3_execution_context 243 244 .if \_secondary_cold_boot 245 /* ------------------------------------------------------------- 246 * Check if this is a primary or secondary CPU cold boot. 247 * The primary CPU will set up the platform while the 248 * secondaries are placed in a platform-specific state until the 249 * primary CPU performs the necessary actions to bring them out 250 * of that state and allows entry into the OS. 251 * ------------------------------------------------------------- 252 */ 253 bl plat_is_my_cpu_primary 254 cbnz w0, do_primary_cold_boot 255 256 /* This is a cold boot on a secondary CPU */ 257 bl plat_secondary_cold_boot_setup 258 /* plat_secondary_cold_boot_setup() is not supposed to return */ 259 bl el3_panic 260 261 do_primary_cold_boot: 262 .endif /* _secondary_cold_boot */ 263 264 /* --------------------------------------------------------------------- 265 * Initialize memory now. Secondary CPU initialization won't get to this 266 * point. 267 * --------------------------------------------------------------------- 268 */ 269 270 .if \_init_memory 271 bl platform_mem_init 272 .endif /* _init_memory */ 273 274 /* --------------------------------------------------------------------- 275 * Init C runtime environment: 276 * - Zero-initialise the NOBITS sections. There are 2 of them: 277 * - the .bss section; 278 * - the coherent memory section (if any). 279 * - Relocate the data section from ROM to RAM, if required. 280 * --------------------------------------------------------------------- 281 */ 282 .if \_init_c_runtime 283#if defined(IMAGE_BL31) || (defined(IMAGE_BL2) && \ 284 ((RESET_TO_BL2 && BL2_INV_DCACHE) || ENABLE_RME)) 285 /* ------------------------------------------------------------- 286 * Invalidate the RW memory used by the BL31 image. This 287 * includes the data and NOBITS sections. This is done to 288 * safeguard against possible corruption of this memory by 289 * dirty cache lines in a system cache as a result of use by 290 * an earlier boot loader stage. If PIE is enabled however, 291 * RO sections including the GOT may be modified during 292 * pie fixup. Therefore, to be on the safe side, invalidate 293 * the entire image region if PIE is enabled. 294 * ------------------------------------------------------------- 295 */ 296#if ENABLE_PIE 297#if SEPARATE_CODE_AND_RODATA 298 adrp x0, __TEXT_START__ 299 add x0, x0, :lo12:__TEXT_START__ 300#else 301 adrp x0, __RO_START__ 302 add x0, x0, :lo12:__RO_START__ 303#endif /* SEPARATE_CODE_AND_RODATA */ 304#else 305 adrp x0, __RW_START__ 306 add x0, x0, :lo12:__RW_START__ 307#endif /* ENABLE_PIE */ 308 adrp x1, __RW_END__ 309 add x1, x1, :lo12:__RW_END__ 310 sub x1, x1, x0 311 bl inv_dcache_range 312#if defined(IMAGE_BL31) && SEPARATE_NOBITS_REGION 313 adrp x0, __NOBITS_START__ 314 add x0, x0, :lo12:__NOBITS_START__ 315 adrp x1, __NOBITS_END__ 316 add x1, x1, :lo12:__NOBITS_END__ 317 sub x1, x1, x0 318 bl inv_dcache_range 319#endif 320#if defined(IMAGE_BL2) && SEPARATE_BL2_NOLOAD_REGION 321 adrp x0, __BL2_NOLOAD_START__ 322 add x0, x0, :lo12:__BL2_NOLOAD_START__ 323 adrp x1, __BL2_NOLOAD_END__ 324 add x1, x1, :lo12:__BL2_NOLOAD_END__ 325 sub x1, x1, x0 326 bl inv_dcache_range 327#endif 328#endif 329#if defined(IMAGE_BL31) 330 adrp x0, __PER_CPU_START__ 331 add x0, x0, :lo12:__PER_CPU_START__ 332 adrp x1, __PER_CPU_END__ 333 add x1, x1, :lo12:__PER_CPU_END__ 334 sub x1, x1, x0 335#if (PLATFORM_NODE_COUNT > 1) 336 mov x9, x1 337#endif /* (PLATFORM_NODE_COUNT > 1) */ 338 bl zeromem 339#if (PLATFORM_NODE_COUNT > 1) 340 /* 341 * Zero-initialize per-cpu sections defined by the platform. 342 * Care must be taken to preserve and retain the clobbered 343 * registers. A standard around the container for per-cpu nodes 344 * is not yet defined. 345 */ 346 mov x10, #1 347 mov x11, #PLATFORM_NODE_COUNT 348 349 1: 350 cmp x10, x11 351 b.hs 2f 352 353 mov x0, x10 354 bl plat_per_cpu_node_base 355 cmn x0, #1 356 b.eq 3f 357 358 /* x1 contains size param */ 359 mov x1, x9 360 bl zeromem 361 362 3: 363 add x10, x10, #1 364 b 1b 365 366 2: 367#endif /* (PLATFORM_NODE_COUNT > 1) */ 368#endif /* defined(IMAGE_BL31) */ 369 370 adrp x0, __BSS_START__ 371 add x0, x0, :lo12:__BSS_START__ 372 373 adrp x1, __BSS_END__ 374 add x1, x1, :lo12:__BSS_END__ 375 sub x1, x1, x0 376 bl zeromem 377 378#if USE_COHERENT_MEM 379 adrp x0, __COHERENT_RAM_START__ 380 add x0, x0, :lo12:__COHERENT_RAM_START__ 381 adrp x1, __COHERENT_RAM_END_UNALIGNED__ 382 add x1, x1, :lo12: __COHERENT_RAM_END_UNALIGNED__ 383 sub x1, x1, x0 384 bl zeromem 385#endif 386 387#if defined(IMAGE_BL1) || \ 388 (defined(IMAGE_BL2) && RESET_TO_BL2 && BL2_IN_XIP_MEM) || \ 389 (defined(IMAGE_BL31) && SEPARATE_RWDATA_REGION) 390 391 adrp x0, __DATA_RAM_START__ 392 add x0, x0, :lo12:__DATA_RAM_START__ 393 adrp x1, __DATA_ROM_START__ 394 add x1, x1, :lo12:__DATA_ROM_START__ 395 adrp x2, __DATA_RAM_END__ 396 add x2, x2, :lo12:__DATA_RAM_END__ 397 sub x2, x2, x0 398 bl memcpy16 399#endif 400 .endif /* _init_c_runtime */ 401 402 /* --------------------------------------------------------------------- 403 * Use SP_EL0 for the C runtime stack. 404 * --------------------------------------------------------------------- 405 */ 406 msr spsel, #0 407 408 /* --------------------------------------------------------------------- 409 * Allocate a stack whose memory will be marked as Normal-IS-WBWA when 410 * the MMU is enabled. There is no risk of reading stale stack memory 411 * after enabling the MMU as only the primary CPU is running at the 412 * moment. 413 * --------------------------------------------------------------------- 414 */ 415 bl plat_set_my_stack 416 417#if STACK_PROTECTOR_ENABLED 418 .if \_init_c_runtime 419 bl update_stack_protector_canary 420 .endif /* _init_c_runtime */ 421#endif 422 .endm 423 424 .macro apply_at_speculative_wa 425#if ERRATA_SPECULATIVE_AT 426 /* 427 * This function expects x30 has been saved. 428 * Also, save x29 which will be used in the called function. 429 */ 430 str x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29] 431 bl save_and_update_ptw_el1_sys_regs 432 ldr x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29] 433#endif 434 .endm 435 436 .macro restore_ptw_el1_sys_regs 437#if ERRATA_SPECULATIVE_AT 438 /* ----------------------------------------------------------- 439 * In case of ERRATA_SPECULATIVE_AT, must follow below order 440 * to ensure that page table walk is not enabled until 441 * restoration of all EL1 system registers. TCR_EL1 register 442 * should be updated at the end which restores previous page 443 * table walk setting of stage1 i.e.(TCR_EL1.EPDx) bits. ISB 444 * ensures that CPU does below steps in order. 445 * 446 * 1. Ensure all other system registers are written before 447 * updating SCTLR_EL1 using ISB. 448 * 2. Restore SCTLR_EL1 register. 449 * 3. Ensure SCTLR_EL1 written successfully using ISB. 450 * 4. Restore TCR_EL1 register. 451 * ----------------------------------------------------------- 452 */ 453 isb 454 ldp x28, x29, [sp, #CTX_ERRATA_SPEC_AT_OFFSET + CTX_ERRATA_SPEC_AT_SCTLR_EL1] 455 msr sctlr_el1, x28 456 isb 457 msr tcr_el1, x29 458#endif 459 .endm 460 461/* ----------------------------------------------------------------- 462 * The below macro reads SCR_EL3 from the context structure to 463 * determine the security state of the context upon ERET. 464 * ------------------------------------------------------------------ 465 */ 466 .macro get_security_state _ret:req, _scr_reg:req 467 ubfx \_ret, \_scr_reg, #SCR_NSE_SHIFT, #1 468 cmp \_ret, #1 469 beq realm_state 470 bfi \_ret, \_scr_reg, #0, #1 471 b end 472 realm_state: 473 mov \_ret, #2 474 end: 475 .endm 476 477/*----------------------------------------------------------------------------- 478 * Helper macro to configure EL3 registers we care about, while executing 479 * at EL3/Root world. Root world has its own execution environment and 480 * needs to have its settings configured to be independent of other worlds. 481 * ----------------------------------------------------------------------------- 482 */ 483 .macro setup_el3_execution_context 484 485 /* --------------------------------------------------------------------- 486 * The following registers need to be part of separate root context 487 * as their values are of importance during EL3 execution. 488 * Hence these registers are overwritten to their intital values, 489 * irrespective of whichever world they return from to ensure EL3 has a 490 * consistent execution context throughout the lifetime of TF-A. 491 * 492 * DAIF.A: Enable External Aborts and SError Interrupts at EL3. 493 * 494 * MDCR_EL3.SDD: Set to one to disable AArch64 Secure self-hosted debug. 495 * Debug exceptions, other than Breakpoint Instruction exceptions, are 496 * disabled from all ELs in Secure state. 497 * 498 * SCR_EL3.EA: Set to one to enable SError interrupts at EL3. 499 * 500 * SCR_EL3.SIF: Set to one to disable instruction fetches from 501 * Non-secure memory. 502 * 503 * PMCR_EL0.DP: Set to one so that the cycle counter, 504 * PMCCNTR_EL0 does not count when event counting is prohibited. 505 * Necessary on PMUv3 <= p7 where MDCR_EL3.{SCCD,MCCD} are not 506 * available. 507 * 508 * CPTR_EL3.EZ: Set to one so that accesses to ZCR_EL3 do not trap 509 * CPTR_EL3.ESM: Set to one so that SME related registers don't trap 510 * 511 * PSTATE.DIT: Set to one to enable the Data Independent Timing (DIT) 512 * functionality, if implemented in EL3. 513 * --------------------------------------------------------------------- 514 */ 515 msr daifclr, #DAIF_ABT_BIT 516 517 mrs x15, mdcr_el3 518 orr x15, x15, #MDCR_SDD_BIT 519 msr mdcr_el3, x15 520 521 mrs x15, scr_el3 522 orr x15, x15, #SCR_EA_BIT 523 orr x15, x15, #SCR_SIF_BIT 524 bic x15, x15, #SCR_TRNDR_BIT 525 msr scr_el3, x15 526 527 mrs x15, pmcr_el0 528 orr x15, x15, #PMCR_EL0_DP_BIT 529 msr pmcr_el0, x15 530 531 mrs x15, cptr_el3 532 orr x15, x15, #CPTR_EZ_BIT 533 orr x15, x15, #ESM_BIT 534 msr cptr_el3, x15 535 536#if ENABLE_FEAT_DIT 537#if ENABLE_FEAT_DIT > 1 538 mrs x15, id_aa64pfr0_el1 539 ubfx x15, x15, #ID_AA64PFR0_DIT_SHIFT, #ID_AA64PFR0_DIT_LENGTH 540 cbz x15, 1f 541#endif 542 mov x15, #DIT_BIT 543 msr DIT, x15 544 1: 545#endif 546 547 isb 548 .endm 549 550#endif /* EL3_COMMON_MACROS_S */ 551