| 2f227d51 | 20-Dec-2019 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge changes from topic "tegra-boot-fixes-121719" into integration
* changes:
Tegra: prepare boot parameters for Trusty
Tegra: per-CPU GIC CPU interface init |
| aeb3d83e | 19-Dec-2019 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "mailbox-fixes" into integration
* changes:
intel: Fix SMC SIP service
intel: Introduce mailbox response length handling
intel: Fix mailbox config return status
inte
Merge changes from topic "mailbox-fixes" into integration
* changes:
intel: Fix SMC SIP service
intel: Introduce mailbox response length handling
intel: Fix mailbox config return status
intel: Mailbox driver logic fixes
plat: intel: Fix FPGA manager on reconfiguration
plat: intel: Fix mailbox send_cmd issue
intel: Modify mailbox's get_config_status
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|
| 90324ef4 | 19-Dec-2019 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge "fdts: a5ds: cleanup enable-method in devicetree" into integration |
| 4d9a3758 | 19-Dec-2019 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge "TF-A: Fix BL2 bug in dynamic configuration initialisation" into integration |
| 5ddcbdd8 | 19-Dec-2019 |
Alexei Fedorov <Alexei.Fedorov@arm.com> |
TF-A: Fix BL2 bug in dynamic configuration initialisation
This patch fixes the bug in BL2 dynamic configuration initialisation
which prevents loading NT_FW_CONFIG image (ref. GENFW-3471).
It also ad
TF-A: Fix BL2 bug in dynamic configuration initialisation
This patch fixes the bug in BL2 dynamic configuration initialisation
which prevents loading NT_FW_CONFIG image (ref. GENFW-3471).
It also adds parentheses around 'if' statement conditions to fix
Coverity defect.
Change-Id: I353566c29b84341887e13bf8098a4fedfc4e00ff
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
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|
| f63e9f4c | 19-Dec-2019 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "fdts: a5ds: add L2 cache node in devicetree" into integration |
| 98ee29c6 | 18-Dec-2019 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "intel: Create SiP service header file" into integration |
| ab3b00fb | 13-Dec-2019 |
Vishnu Banavath <vishnu.banavath@arm.com> |
fdts: a5ds: cleanup enable-method in devicetree
Same enable method is used by all the four cores. So,
make it globally for all the cores instead of adding
it to individual level.
Change-Id: I9b5728
fdts: a5ds: cleanup enable-method in devicetree
Same enable method is used by all the four cores. So,
make it globally for all the cores instead of adding
it to individual level.
Change-Id: I9b5728b0e0545c9e27160ea586009d929eb78cad
Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>
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|
| 79c6c342 | 13-Dec-2019 |
Vishnu Banavath <vishnu.banavath@arm.com> |
fdts: a5ds: add L2 cache node in devicetree
This change is to add L2 cache node into a5ds device tree.
Change-Id: I64b4b3e839c3ee565abbcd1567d1aa358c32d947
Signed-off-by: Vishnu Banavath <vishnu.ba
fdts: a5ds: add L2 cache node in devicetree
This change is to add L2 cache node into a5ds device tree.
Change-Id: I64b4b3e839c3ee565abbcd1567d1aa358c32d947
Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>
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|
| 31645dde | 18-Dec-2019 |
Mark Dykes <mardyk01@review.trustedfirmware.org> |
Merge "drivers: marvell: comphy-a3700: support SGMII COMPHY power off" into integration |
| 2783205d | 18-Dec-2019 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra: prepare boot parameters for Trusty
This patch saves the boot parameters provided by the previous bootloader
during cold boot and passes them to Trusty. Commit 06ff251ec introduced
the plat_tr
Tegra: prepare boot parameters for Trusty
This patch saves the boot parameters provided by the previous bootloader
during cold boot and passes them to Trusty. Commit 06ff251ec introduced
the plat_trusty_set_boot_args() handler, but did not consider the boot
parameters passed by the previous bootloader. This patch fixes that
anomaly.
Change-Id: Ib40dcd02b67c94cea5cefce09edb0be4a998db37
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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|
| 90a76bab | 18-Dec-2019 |
Mark Dykes <mardyk01@review.trustedfirmware.org> |
Merge "drivers: marvell: comphy-a3700: fix USB3 powering on when on lane 2" into integration |
| 4962385e | 18-Dec-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge changes from topic "nonbl2-boot" into integration
* changes:
intel: stratix10: Modify BL31 parameter handling
intel: Modify BL31 address mapping
intel: stratix10: Enable uboot entrypoint
Merge changes from topic "nonbl2-boot" into integration
* changes:
intel: stratix10: Modify BL31 parameter handling
intel: Modify BL31 address mapping
intel: stratix10: Enable uboot entrypoint support
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|
| cd07df8c | 18-Dec-2019 |
Alexei Fedorov <Alexei.Fedorov@arm.com> |
Merge "aarch64: Fix stack pointer maintenance on EA handling path" into integration |
| 992f091b | 12-Jul-2019 |
Ambroise Vincent <ambroise.vincent@arm.com> |
debugfs: add SMC channel
Provide an SMC interface to the 9p filesystem. This permits
accessing firmware drivers through a common interface, using
standardized read/write/control operations.
Signed-
debugfs: add SMC channel
Provide an SMC interface to the 9p filesystem. This permits
accessing firmware drivers through a common interface, using
standardized read/write/control operations.
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I9314662314bb060f6bc02714476574da158b2a7d
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|
| bb9549ba | 02-Dec-2019 |
Jan Dabros <jsd@semihalf.com> |
aarch64: Fix stack pointer maintenance on EA handling path
EA handlers for exceptions taken from lower ELs at the end invokes
el3_exit function. However there was a bug with sp maintenance which
res
aarch64: Fix stack pointer maintenance on EA handling path
EA handlers for exceptions taken from lower ELs at the end invokes
el3_exit function. However there was a bug with sp maintenance which
resulted in el3_exit setting runtime stack to context. This in turn
caused memory corruption on consecutive EL3 entries.
Signed-off-by: Jan Dabros <jsd@semihalf.com>
Change-Id: I0424245c27c369c864506f4baa719968890ce659
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|
| e9e19fb2 | 17-Dec-2019 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra: per-CPU GIC CPU interface init
This patch enables per-CPU GIC CPU interfaces during CPU
power on. The previous code initialized the distributor
for all CPUs, which was not required.
Signed-o
Tegra: per-CPU GIC CPU interface init
This patch enables per-CPU GIC CPU interfaces during CPU
power on. The previous code initialized the distributor
for all CPUs, which was not required.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: Ifd957b2367da06405b4c3e2225411adbaec35bb8
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|
| 0d35873c | 17-Dec-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge changes from topic "allwinner_pmic" into integration
* changes:
allwinner: h6: power: Switch to using the AXP driver
drivers: allwinner: axp: Add AXP805 support |
| 4e0d14f2 | 17-Dec-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge "arm: gicv3: Fix compiler dependent behavior" into integration |
| 287a81df | 17-Dec-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge "plat/rockchip: enable power domains of rk3399 before reset" into integration |
| 37ebe8e5 | 17-Dec-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge "plat/rockchip: cliam a macro to enable hdcp feature for DP" into integration |
| 0531ada5 | 07-Nov-2019 |
Bence Szépkúti <bence.szepkuti@arm.com> |
pmf: Make the runtime instrumentation work on AArch32
Ported the pmf asm macros and the asm code in the bl31 entrypoint
necessary for the instrumentation to AArch32.
Since smc dispatch is handled b
pmf: Make the runtime instrumentation work on AArch32
Ported the pmf asm macros and the asm code in the bl31 entrypoint
necessary for the instrumentation to AArch32.
Since smc dispatch is handled by the bl32 payload on AArch32, we
provide this service only if AARCH32_SP=sp_min is set.
Signed-off-by: Bence Szépkúti <bence.szepkuti@arm.com>
Change-Id: Id33b7e9762ae86a4f4b40d7f1b37a90e5130c8ac
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|
| 9d725191 | 24-Oct-2019 |
Bence Szépkúti <bence.szepkuti@arm.com> |
SiP: Don't validate entrypoint if state switch is impossible
Switching execution states is only possible if EL3 is AArch64.
As such there is no need to validate the entrypoint on AArch32 builds.
Si
SiP: Don't validate entrypoint if state switch is impossible
Switching execution states is only possible if EL3 is AArch64.
As such there is no need to validate the entrypoint on AArch32 builds.
Signed-off-by: Bence Szépkúti <bence.szepkuti@arm.com>
Change-Id: I3c1eb25b5df296a492870641d274bf65213c6608
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| 4c4cff6b | 20-Oct-2019 |
Simon South <simon@simonsouth.net> |
rockchip: rk3328: Enable workaround for erratum 855873
Enable the workaround for Cortex-A53 erratum 855873 for the Rockchip
RK3328, silencing a warning at startup.
Change-Id: I5aa29d674d23c096c599a
rockchip: rk3328: Enable workaround for erratum 855873
Enable the workaround for Cortex-A53 erratum 855873 for the Rockchip
RK3328, silencing a warning at startup.
Change-Id: I5aa29d674d23c096c599abcb5e7dac970f9607d8
Signed-off-by: Simon South <simon@simonsouth.net>
show more ...
|
| 7c58fd4e | 12-Nov-2019 |
Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> |
intel: Fix SMC SIP service
Fix FPGA reconfiguration driver logic
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I0299c1a71f3456e9b441340314662494b8d3e4a0 |