1/* 2 * Copyright (c) 2019, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7/dts-v1/; 8 9/ { 10 model = "A5DS"; 11 compatible = "arm,A5DS"; 12 interrupt-parent = <&gic>; 13 #address-cells = <1>; 14 #size-cells = <1>; 15 16 psci { 17 compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci"; 18 method = "smc"; 19 cpu_on = <0x84000003>; 20 }; 21 22 cpus { 23 #address-cells = <1>; 24 #size-cells = <0>; 25 cpu@0 { 26 device_type = "cpu"; 27 compatible = "arm,cortex-a5"; 28 enable-method = "psci"; 29 reg = <0>; 30 next-level-cache = <&L2>; 31 }; 32 cpu@1 { 33 device_type = "cpu"; 34 compatible = "arm,cortex-a5"; 35 enable-method = "psci"; 36 reg = <1>; 37 next-level-cache = <&L2>; 38 }; 39 cpu@2 { 40 device_type = "cpu"; 41 compatible = "arm,cortex-a5"; 42 enable-method = "psci"; 43 reg = <2>; 44 next-level-cache = <&L2>; 45 }; 46 cpu@3 { 47 device_type = "cpu"; 48 compatible = "arm,cortex-a5"; 49 enable-method = "psci"; 50 reg = <3>; 51 next-level-cache = <&L2>; 52 }; 53 }; 54 55 memory@80000000 { 56 device_type = "memory"; 57 reg = <0x80000000 0x7F000000>; 58 }; 59 60 L2: cache-controller@1C010000 { 61 compatible = "arm,pl310-cache"; 62 reg = <0x1C010000 0x1000>; 63 interrupts = <0 84 4>; 64 cache-level = <2>; 65 cache-unified; 66 arm,data-latency = <1 1 1>; 67 arm,tag-latency = <1 1 1>; 68 }; 69 70 refclk100mhz: refclk100mhz { 71 compatible = "fixed-clock"; 72 #clock-cells = <0>; 73 clock-frequency = <100000000>; 74 clock-output-names = "apb_pclk"; 75 }; 76 77 smbclk: refclk24mhzx2 { 78 compatible = "fixed-clock"; 79 #clock-cells = <0>; 80 clock-frequency = <48000000>; 81 clock-output-names = "smclk"; 82 }; 83 84 85 rtc@1a220000 { 86 compatible = "arm,pl031", "arm,primecell"; 87 reg = <0x1a220000 0x1000>; 88 clocks = <&refclk100mhz>; 89 interrupts = <0 6 0xf04>; 90 clock-names = "apb_pclk"; 91 }; 92 93 gic: interrupt-controller@1c001000 { 94 compatible = "arm,cortex-a9-gic"; 95 #interrupt-cells = <3>; 96 #address-cells = <0>; 97 interrupt-controller; 98 reg = <0x1c001000 0x1000>, 99 <0x1c000100 0x100>; 100 interrupts = <1 9 0xf04>; 101 }; 102 103 serial0: uart@1a200000 { 104 compatible = "arm,pl011", "arm,primecell"; 105 reg = <0x1a200000 0x1000>; 106 interrupt-parent = <&gic>; 107 interrupts = <0 8 0xf04>; 108 clocks = <&refclk100mhz>; 109 clock-names = "apb_pclk"; 110 }; 111 112 serial1: uart@1a210000 { 113 compatible = "arm,pl011", "arm,primecell"; 114 reg = <0x1a210000 0x1000>; 115 interrupt-parent = <&gic>; 116 interrupts = <0 9 0xf04>; 117 clocks = <&refclk100mhz>; 118 clock-names = "apb_pclk"; 119 }; 120 121 timer0: timer@1a040000 { 122 compatible = "arm,armv7-timer-mem"; 123 #address-cells = <1>; 124 #size-cells = <1>; 125 ranges; 126 reg = <0x1a040000 0x1000>; 127 clock-frequency = <50000000>; 128 129 frame@1a050000 { 130 frame-number = <0>; 131 interrupts = <0 2 0xf04>; 132 reg = <0x1a050000 0x1000>; 133 }; 134 }; 135}; 136