plat/rockchip: cliam a macro to enable hdcp feature for DP

HDCP is using a binary driver, add macro PLAT_RK_DP_HDCP to make it as
an option.

Change-Id: I54ef1a3635a28e8ae56654bd1e91dfe011520a7f
Sig

plat/rockchip: cliam a macro to enable hdcp feature for DP

HDCP is using a binary driver, add macro PLAT_RK_DP_HDCP to make it as
an option.

Change-Id: I54ef1a3635a28e8ae56654bd1e91dfe011520a7f
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>

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Remove -Wmissing-declarations warning from WARNING1 level

A function declaration declares the name of the function and the type of
the parameter it returns. A function prototype is a function declar

Remove -Wmissing-declarations warning from WARNING1 level

A function declaration declares the name of the function and the type of
the parameter it returns. A function prototype is a function declaration
that also specifies the type of the arguments of the function. Essentially,
a function prototype helps the compiler ensure whether the function call
matches the return type and the right number/type of arguments of function.
A function prototype itself serves as a function declaration for new style
functions.
The warning flag -wmissing-prototype is good enough to check for missing
function prototype and is exhaustive compared to -wmissing-declaration,
therefore making the later redundant.

Note that, at this point, these flags are part of WARNING1 which is not
used for TF-A build by default. Several platforms use upstream libraries
(such as zlib etc) which are in old style c code. After the TF-A build
process is restructred using CMake framework, we plan to enable WARNING1,
WARNING2 and WARNING3 incrementally as the new build platform can compile
each BL binary of a particular platform with set of unique compilation
flags.

Change-Id: I9c6bf9da74e0840e4d2624bc12376e199953c213
Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>

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Merge changes from topic "enable-tegra194-compilation" into integration

* changes:
docs: tegra: add support for Tegra194 class of SoCs
Tegra194: smmu: add support for backup multiple smmu regs

Merge changes from topic "enable-tegra194-compilation" into integration

* changes:
docs: tegra: add support for Tegra194 class of SoCs
Tegra194: smmu: add support for backup multiple smmu regs
Tegra194: introduce tegra_mc_def.h
Tegra194: 40-bit wide memory address space
Tegra194: psci: rename 'percpu_data' variable

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Merge "PIE: make call to GDT relocation fixup generalized" into integration

PIE: make call to GDT relocation fixup generalized

When a Firmware is complied as Position Independent Executable it needs
to request GDT fixup by passing size of the memory region to
el3_entrypoint

PIE: make call to GDT relocation fixup generalized

When a Firmware is complied as Position Independent Executable it needs
to request GDT fixup by passing size of the memory region to
el3_entrypoint_common macro.
The Global descriptor table fixup will be done early on during cold boot
process of primary core.

Currently only BL31 supports PIE, but in future when BL2_AT_EL3 will be
compiled as PIE, it can simply pass fixup size to the common el3
entrypoint macro to fixup GDT.

The reason for this patch was to overcome the bug introduced by SHA
330ead806 which called fixup routine for each core causing
re-initializing of global pointers thus overwriting any changes
done by the previous core.

Change-Id: I55c792cc3ea9e7eef34c2e4653afd04572c4f055
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>

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intel: s10: Remove unused source code

remove plat_sip_svc.c and plat_psci.c in stratix 10 platform directory
as both has been refactored to common directory for sharing with agilex
platform

Signed-

intel: s10: Remove unused source code

remove plat_sip_svc.c and plat_psci.c in stratix 10 platform directory
as both has been refactored to common directory for sharing with agilex
platform

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I395fed66408f536e8fefd637681e742c63621818

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drivers: marvell: comphy-a3700: support SGMII COMPHY power off

Add support for powering off the SGMII COMPHY (on lanes 0 and 1).
This is needed sometimes on Turris Mox when using KEXEC.

There is al

drivers: marvell: comphy-a3700: support SGMII COMPHY power off

Add support for powering off the SGMII COMPHY (on lanes 0 and 1).
This is needed sometimes on Turris Mox when using KEXEC.

There is also another benefit of a little energy saving when the given
network interface is down.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: I55ae0fe3627e7cc0f65c78a00771939d8bf5399f

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drivers: marvell: comphy-a3700: fix USB3 powering on when on lane 2

When USB3 is on lane 2 and indirect register access is used, the polling
at the end of the mvebu_a3700_comphy_usb3_power_on functi

drivers: marvell: comphy-a3700: fix USB3 powering on when on lane 2

When USB3 is on lane 2 and indirect register access is used, the polling
at the end of the mvebu_a3700_comphy_usb3_power_on function is
incorrect.

The LOOPBACK_REG0 register should not be used at all. Instead we have to
write the LANE_STATUS1 register address (with offset
USB3PHY_LANE2_REG_BASE_OFFSET) into the indirect address register and
then we should poll indirect data register.

This fixes problems on Turris Mox, which uses lane 2 for USB3.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: I968b0cccee5ddbe10a2b5614e52e52d87682aacd

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cryptocell: add cryptocell 712 RSA 3K support

Add the support needed to enable using CryptoCell integration with
with RSA 3K support.

Signed-off-by: Gilad Ben-Yossef <gilad.benyossef@arm.com>
Chang

cryptocell: add cryptocell 712 RSA 3K support

Add the support needed to enable using CryptoCell integration with
with RSA 3K support.

Signed-off-by: Gilad Ben-Yossef <gilad.benyossef@arm.com>
Change-Id: I95527cb0c41ae012109e8968dd20a4ae9fe67f17

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Merge "libc: add memrchr" into integration

libc: add memrchr

This function scans a string backwards from the end for the first
instance of a character.

Change-Id: I46b21573ed25a0ff222eac340e1e1fb93b040763
Signed-off-by: Ambroise Vincent <am

libc: add memrchr

This function scans a string backwards from the end for the first
instance of a character.

Change-Id: I46b21573ed25a0ff222eac340e1e1fb93b040763
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>

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arm: gicv3: Fix compiler dependent behavior

C99 standard: "What constitutes an access to an object that has
volatile-qualified type is implementation-defined".

GCC is not considering the cast to vo

arm: gicv3: Fix compiler dependent behavior

C99 standard: "What constitutes an access to an object that has
volatile-qualified type is implementation-defined".

GCC is not considering the cast to void of volatile structures as an
access and so is not actually issuing reads.

Clang does read those structures by copying them on the stack, which in
this case creates an overflow because of their large size.

This patch removes the cast to void and instead uses the USED attribute
to tell the compiler to retain the static variables.

Change-Id: I952b5056e3f6e91841e7ef9558434352710ab80d
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
Zelalem Aweke <zelalem.aweke@arm.com>

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plat/rockchip: enable power domains of rk3399 before reset

This patch fixes hangs that happen after soft resetting of rk3399.

Signed-off-by: Piotr Szczepanik <piter75@gmail.com>
Change-Id: If41b12b

plat/rockchip: enable power domains of rk3399 before reset

This patch fixes hangs that happen after soft resetting of rk3399.

Signed-off-by: Piotr Szczepanik <piter75@gmail.com>
Change-Id: If41b12ba1dfcb2ba937361b58eafd50bf5c483d4

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docs: tegra: add support for Tegra194 class of SoCs

This patch adds the Tegra194 SoC information to the nvidia-tegra.rst
file.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: Id649a5f

docs: tegra: add support for Tegra194 class of SoCs

This patch adds the Tegra194 SoC information to the nvidia-tegra.rst
file.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: Id649a5ff1b3f70eeee34b508edb7965e7b7a2454

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Tegra194: smmu: add support for backup multiple smmu regs

Tegra194 supports multiple SMMU blocks. This patch adds support to
save register values for SMMU0 and SMMU2, before entering the System
Susp

Tegra194: smmu: add support for backup multiple smmu regs

Tegra194 supports multiple SMMU blocks. This patch adds support to
save register values for SMMU0 and SMMU2, before entering the System
Suspend state.

Change-Id: I3a376cdb606ea057ad7047714717245f9dced5cf
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>

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Tegra194: introduce tegra_mc_def.h

This patch introduces memory controller register defines
for Tegra194 platforms.

Change-Id: I6596341ae817b6cec30cb74d201ad854a0c8c0a6
Signed-off-by: Pritesh Raith

Tegra194: introduce tegra_mc_def.h

This patch introduces memory controller register defines
for Tegra194 platforms.

Change-Id: I6596341ae817b6cec30cb74d201ad854a0c8c0a6
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>

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Tegra194: 40-bit wide memory address space

This patch updates the memory address space, physical and virtual,
to be 40-bits wide for all Tegra194 platforms.

Change-Id: Ie1bcdec2c4e8e15975048ce1c2a3

Tegra194: 40-bit wide memory address space

This patch updates the memory address space, physical and virtual,
to be 40-bits wide for all Tegra194 platforms.

Change-Id: Ie1bcdec2c4e8e15975048ce1c2a31c2ae0dd494c
Signed-off-by: Steven Kao <skao@nvidia.com>

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Tegra194: psci: rename 'percpu_data' variable

The per CPU wake times are saved in an array called 't19x_percpu_data'. But,
there is one instance in the code where the name of the variable is misspel

Tegra194: psci: rename 'percpu_data' variable

The per CPU wake times are saved in an array called 't19x_percpu_data'. But,
there is one instance in the code where the name of the variable is misspelt.

This patch fixes this typographical error to fix compilation errors.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I52f5f0b150c51d8cc38372675415dec7944a7735

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Merge "adding support to enable different personality of the same soc." into integration

Merge "Use the proper size for tb_fw_cfg_dtb" into integration

Merge "arm: Fix current RECLAIM_INIT_CODE behavior" into integration

arm: Fix current RECLAIM_INIT_CODE behavior

Previously the .init section was created even when the reclaim flag was
manually set to 0.

Change-Id: Ia9e7c7997261f54a4eca725d7ea605192f60bcf8
Signed-of

arm: Fix current RECLAIM_INIT_CODE behavior

Previously the .init section was created even when the reclaim flag was
manually set to 0.

Change-Id: Ia9e7c7997261f54a4eca725d7ea605192f60bcf8
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
Zelalem Aweke <zelalem.aweke@arm.com>

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Merge changes from topic "lm/memmap" into integration

* changes:
Add memory_map tools as a target for Make
tools: Add show_memory script

Use the proper size for tb_fw_cfg_dtb

Currently tb_fw_cfg_dtb size is fixed to max, which is generally a page
(but depend on the platform). Instead, read the actual size of the dtb
with the libfdt "

Use the proper size for tb_fw_cfg_dtb

Currently tb_fw_cfg_dtb size is fixed to max, which is generally a page
(but depend on the platform). Instead, read the actual size of the dtb
with the libfdt "fdt_totalsize" function.
This avoid flushing extra memory after updating the dtb with mbedtls
heap information when shared heap is used.

Change-Id: Ibec727661116429f486464a0c9f15e9760d7afe2
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>

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rpi3/4: Add support for offlining CPUs

The hooks were populated but the power down left the CPU in limbo-land.
What we need to do - until there is a way to actually power off - is to
turn off the MM

rpi3/4: Add support for offlining CPUs

The hooks were populated but the power down left the CPU in limbo-land.
What we need to do - until there is a way to actually power off - is to
turn off the MMU and enter the spinning loop as if we were cold-booted.
This allows the on-call to pick up the CPU again.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Change-Id: Iefc7a58424e3578ad3dd355a7bd6eaba4b412699

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