rcar_gen3: drivers: ddr: Update DDR setting for H3, M3, M3N

[IPL/DDR]
- Update H3, M3, M3N DDR setting rev.0.38.

Signed-off-by: Chiaki Fujii <chiaki.fujii.wj@renesas.com>
Signed-off-by: Marek Vasut

rcar_gen3: drivers: ddr: Update DDR setting for H3, M3, M3N

[IPL/DDR]
- Update H3, M3, M3N DDR setting rev.0.38.

Signed-off-by: Chiaki Fujii <chiaki.fujii.wj@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> # upstream update
Change-Id: I49cf8f778b849a6ee97bc9f6948c45b07dc467b1

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rcar_gen3: plat: Update IPL and Secure Monitor Rev.2.0.5

Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Sig

rcar_gen3: plat: Update IPL and Secure Monitor Rev.2.0.5

Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> # upstream update
Change-Id: I8ef32a67f7984d8bcfcc3655988b559efa6e65ab

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rcar_gen3: plat: Change fixed destination address of BL31 and BL32

This patch changes the destination address of BL31 and BL32 From
fixed address for getting from the each certificates.

Signed-off-

rcar_gen3: plat: Change fixed destination address of BL31 and BL32

This patch changes the destination address of BL31 and BL32 From
fixed address for getting from the each certificates.

Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> # upstream rework
Change-Id: Ide11776feff25e6fdd55ab28503a15b658b2e0d5

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Merge "Fix topology description of cpus for DynamIQ based FVP" into integration

tools: Small improvement to print_memory_map script

This patch:
- Add the __COHERENT_RAM_START__ and __COHERENT_RAM_END__ symbols.
- Improve how the symbols are found with a regex.
- Add a build opt

tools: Small improvement to print_memory_map script

This patch:
- Add the __COHERENT_RAM_START__ and __COHERENT_RAM_END__ symbols.
- Improve how the symbols are found with a regex.
- Add a build option to revert the memory layout output.

Change-Id: I54ec660261431bc98d78acb0f80e3d95bc5397ac
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>

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Merge "fconf: Move remaining arm platform to fconf" into integration

Merge changes from topic "uniphier" into integration

* changes:
uniphier: make I/O register region configurable
uniphier: make PSCI related base address configurable
uniphier: make counter con

Merge changes from topic "uniphier" into integration

* changes:
uniphier: make I/O register region configurable
uniphier: make PSCI related base address configurable
uniphier: make counter control base address configurable
uniphier: make UART base address configurable
uniphier: make pinmon base address configurable
uniphier: make NAND controller base address configurable
uniphier: make eMMC controller base address configurable

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mediatek: mt8183: protect 4GB~8GB dram memory

The offset there is the virtual address space on the bus side (1-9GB for 8GB RAM),
and that emi_mpu_set_region_protection will translate to the physical

mediatek: mt8183: protect 4GB~8GB dram memory

The offset there is the virtual address space on the bus side (1-9GB for 8GB RAM),
and that emi_mpu_set_region_protection will translate to the physical memory space (0-8GB).

8GB is 33-bit (the memory bus width is 33-bit on this platform),
so 0x23FFFFFFFUL-EMI_PHY_OFFSET = 0x1_FFFF_FFFF.

Change-Id: I7be4759ed7546f7e15a5868b6f08988928c34075
Signed-off-by: Xi Chen <xixi.chen@mediatek.com>

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Fix topology description of cpus for DynamIQ based FVP

DynamIQ based designs have upto 8 CPUs in each cluster. This
patch fixes the device tree node which describes the topology
of the CPU for Dynam

Fix topology description of cpus for DynamIQ based FVP

DynamIQ based designs have upto 8 CPUs in each cluster. This
patch fixes the device tree node which describes the topology
of the CPU for DynamIQ FVP Model.

Change-Id: I7146bc79029ce38314026d4853e5b6406863725c
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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Merge "corstone700: adding support for stack protector for the FVP" into integration

corstone700: adding support for stack protector for the FVP

Adding support for generating a semi-random number required for
enabling building TF-A with stack protector support.
TF-A for corstone-700

corstone700: adding support for stack protector for the FVP

Adding support for generating a semi-random number required for
enabling building TF-A with stack protector support.
TF-A for corstone-700 may now be built using ENABLE_STACK_PROTECTOR=all

Change-Id: I03e1be1a8d4e4a822cf286f3b9ad4da4337ca765
Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>

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Merge changes from topic "uniphier" into integration

* changes:
uniphier: extend boot device detection for future SoCs
uniphier: change block_addressing flag to bool
uniphier: change the retur

Merge changes from topic "uniphier" into integration

* changes:
uniphier: extend boot device detection for future SoCs
uniphier: change block_addressing flag to bool
uniphier: change the return value type of .is_usb_boot() to bool

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allwinner: Implement PSCI system suspend using SCPI

If an SCP firmware is present and able to communicate via SCPI, then use
that to implement CPU and system power state transitions, including CPU
h

allwinner: Implement PSCI system suspend using SCPI

If an SCP firmware is present and able to communicate via SCPI, then use
that to implement CPU and system power state transitions, including CPU
hotplug and system suspend. Otherwise, fall back to the existing CPU
power control implementation.

The last 16 KiB of SRAM A2 are reserved for the SCP firmware, and the
SCPI shared memory is at the very end of this region (and therefore the
end of SRAM A2). BL31 continues to start at the beginning of SRAM A2
(not counting the ARISC exception vector area) and fills up to the
beginning of the SCP firmware.

Because the SCP firmware is not loaded adjacent to the ARISC exception
vector area, the jump instructions used for exception handling cannot be
included in the SCP firmware image, and must be initialized here before
turning on the SCP.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: I37b9b9636f94d4125230423726f3ac5e9cdb551c

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allwinner: Add a msgbox driver for use with SCPI

The function names follow the naming convention used by the existing
ARM SCPI client.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id:

allwinner: Add a msgbox driver for use with SCPI

The function names follow the naming convention used by the existing
ARM SCPI client.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: I543bae7d46e206eb405dbedfcf7aeba88a12ca48

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allwinner: Reserve and map space for the SCP firmware

The SCP firmware is allocated the last 16KiB of SRAM A2. This includes
the SCPI shared memory area, which must be mapped as MT_DEVICE to
prevent

allwinner: Reserve and map space for the SCP firmware

The SCP firmware is allocated the last 16KiB of SRAM A2. This includes
the SCPI shared memory area, which must be mapped as MT_DEVICE to
prevent problems with cache coherency between the AP CPUs and the SCP.
For simplicity, map the whole SCP region as MT_DEVICE.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Ie39eb5ff281b8898a3c1d9748dc08755f528e2f8

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allwinner: Adjust SRAM A2 base to include the ARISC vectors

The ARISC vector area consists of 0x4000 bytes before the beginning of
usable SRAM. Still, it is technically a part of SRAM A2, so include

allwinner: Adjust SRAM A2 base to include the ARISC vectors

The ARISC vector area consists of 0x4000 bytes before the beginning of
usable SRAM. Still, it is technically a part of SRAM A2, so include it
in the memory definition. This avoids the confusing practice of
subtracting from the beginning of the SRAM region when referencing the
ARISC vectors.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Iae89e01aeab93560159562692e03e88306e2a1bf

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arm/css/scpi: Don't panic if the SCP fails to respond

Instead, pass back the error to the calling function. This allows
platform code to fall back to another PSCI implementation if
scpi_wait_ready()

arm/css/scpi: Don't panic if the SCP fails to respond

Instead, pass back the error to the calling function. This allows
platform code to fall back to another PSCI implementation if
scpi_wait_ready() or a later SCPI command fails.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Ib4411e63c2512857f09ffffe1c405358dddeb4a6

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Fix boot failures on some builds linked with ld.lld.

Pad the .rodata section to 16 bytes as ld.lld does not apply the ALIGN
statement on the .data section to the LMA. Fixes boot failure on builds
wh

Fix boot failures on some builds linked with ld.lld.

Pad the .rodata section to 16 bytes as ld.lld does not apply the ALIGN
statement on the .data section to the LMA. Fixes boot failure on builds
where the .rodata section happens to not be 16 bytes aligned.

Change-Id: I4e95678f73d8b326c5fc749dc7d0ce84e2d603f5
Signed-off-by: Arve Hjønnevåg <arve@android.com>

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trusty: generic-arm64-smcall: Support gicr address

Add SMC_GET_GIC_BASE_GICR option to SMC_FC_GET_REG_BASE and
SMC_FC64_GET_REG_BASE calls for returning the base address of the gic
redistributor add

trusty: generic-arm64-smcall: Support gicr address

Add SMC_GET_GIC_BASE_GICR option to SMC_FC_GET_REG_BASE and
SMC_FC64_GET_REG_BASE calls for returning the base address of the gic
redistributor added in gic version 3.

Bug: 122357256
Change-Id: Ia7c287040656515bab262588163e0c5fc8f13a21
Signed-off-by: Arve Hjønnevåg <arve@android.com>

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trusty: Allow gic base to be specified with GICD_BASE

Some platforms define GICD_BASE instead of PLAT_ARM_GICD_BASE but the
meaning is the same.

Change-Id: I1bb04bb49fdab055b365b1d70a4d48d2058e49df

trusty: Allow gic base to be specified with GICD_BASE

Some platforms define GICD_BASE instead of PLAT_ARM_GICD_BASE but the
meaning is the same.

Change-Id: I1bb04bb49fdab055b365b1d70a4d48d2058e49df
Signed-off-by: Arve Hjønnevåg <arve@android.com>

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trusty: Allow getting trusty memsize from BL32_MEM_SIZE instead of TSP_SEC_MEM_SIZE

Some platforms define BL32_MEM_SIZE instead of TSP_SEC_MEM_SIZE, but
the meaning is the same.

Change-Id: I93d96dc

trusty: Allow getting trusty memsize from BL32_MEM_SIZE instead of TSP_SEC_MEM_SIZE

Some platforms define BL32_MEM_SIZE instead of TSP_SEC_MEM_SIZE, but
the meaning is the same.

Change-Id: I93d96dca442e653435cae6a165b1955efe2d2b75
Signed-off-by: Arve Hjønnevåg <arve@android.com>

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Fix clang build if CC is not in the path.

If CC points to clang the linker was set to ld.lld. Copy the diectory
name from CC is it has one.

Change-Id: I50aef5dddee4d2540b12b6d4e68068ad004446f7
Sign

Fix clang build if CC is not in the path.

If CC points to clang the linker was set to ld.lld. Copy the diectory
name from CC is it has one.

Change-Id: I50aef5dddee4d2540b12b6d4e68068ad004446f7
Signed-off-by: Arve Hjønnevåg <arve@android.com>

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Merge "doc: debugfs remove references section and add topic to components index" into integration

Merge "intel: Change boot source selection" into integration

Merge changes Ib68092d1,I816ea14e into integration

* changes:
plat: marvell: armada: scp_bl2: allow loading up to 8 images
plat: marvell: armada: add support for loading MG CM3 images