| fcfa15d4 | 22-Sep-2023 |
Lauren Wehrmeister <lauren.wehrmeister@arm.com> |
Merge changes from topic "errata" into integration
* changes:
fix(cpus): workaround for Neoverse V2 erratum 2743011
fix(cpus): workaround for Neoverse V2 erratum 2779510
fix(cpus): workaround
Merge changes from topic "errata" into integration
* changes:
fix(cpus): workaround for Neoverse V2 erratum 2743011
fix(cpus): workaround for Neoverse V2 erratum 2779510
fix(cpus): workaround for Neoverse V2 erratum 2719105
fix(cpus): workaround for Neoverse V2 erratum 2331132
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| 5c8fcc0c | 20-Sep-2023 |
Sona Mathew <sonarebecca.mathew@arm.com> |
fix(errata-abi): fix the rev-var for Cortex-A710
Update the revision and variant information in the
errata ABI file for Cortex-A710, erratum ID - 2058056
to match the revision and variant in the cor
fix(errata-abi): fix the rev-var for Cortex-A710
Update the revision and variant information in the
errata ABI file for Cortex-A710, erratum ID - 2058056
to match the revision and variant in the cortex_a710.S
file.
Change-Id: I4b974ac1f94d770f3ae7c15c88f42380c944eb43
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
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| 58dd153c | 19-Sep-2023 |
Bipin Ravi <bipin.ravi@arm.com> |
fix(cpus): workaround for Neoverse V2 erratum 2743011
Neoverse V2 erratum 2743011 is a Cat B erratum that applies to
all revisions <= r0p1 and is fixed in r0p2. The workaround is to
set CPUACTLR5_EL
fix(cpus): workaround for Neoverse V2 erratum 2743011
Neoverse V2 erratum 2743011 is a Cat B erratum that applies to
all revisions <= r0p1 and is fixed in r0p2. The workaround is to
set CPUACTLR5_EL1[56:55] to 2'b01.
SDEN documentation:
https://developer.arm.com/documentation/SDEN2332927/latest
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I0e06ca723a1cce51fb027b7160f3dd06a4c93e64
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| ff342643 | 19-Sep-2023 |
Bipin Ravi <bipin.ravi@arm.com> |
fix(cpus): workaround for Neoverse V2 erratum 2779510
Neoverse V2 erratum 2779510 is a Cat B erratum that applies to
all revisions <= r0p1 and is fixed in r0p2. The workaround is to
set bit[47] of C
fix(cpus): workaround for Neoverse V2 erratum 2779510
Neoverse V2 erratum 2779510 is a Cat B erratum that applies to
all revisions <= r0p1 and is fixed in r0p2. The workaround is to
set bit[47] of CPUACTLR3_EL1 which might have a small impact on
power and negligible impact on performance.
SDEN documentation:
https://developer.arm.com/documentation/SDEN2332927/latest
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I6d937747bdcbf2913a64c4037f99918cbc466e80
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| b0114025 | 18-Sep-2023 |
Bipin Ravi <bipin.ravi@arm.com> |
fix(cpus): workaround for Neoverse V2 erratum 2719105
Neoverse V2 erratum 2719105 is a Cat B erratum that applies to all
revisions <= r0p1 and is fixed in r0p2.
The erratum is avoided by setting CP
fix(cpus): workaround for Neoverse V2 erratum 2719105
Neoverse V2 erratum 2719105 is a Cat B erratum that applies to all
revisions <= r0p1 and is fixed in r0p2.
The erratum is avoided by setting CPUACTLR2_EL1[0] to 1 to force
PLDW/PFRM ST to behave like PLD/PRFM LD and not cause invalidations
to other PE caches. There might be a small performance degradation
to this workaround for certain workloads that share data.
SDEN documentation:
https://developer.arm.com/documentation/SDEN2332927/latest
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: Id026edcb7ee1ca93371ce0001d18f5a8282c49ba
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| 8852fb5b | 18-Sep-2023 |
Bipin Ravi <bipin.ravi@arm.com> |
fix(cpus): workaround for Neoverse V2 erratum 2331132
Neoverse V2 erratum 2331132 is a Cat B erratum that applies to all
revisions <= r0p2 and is still open. The workaround is to write the
value 4'b
fix(cpus): workaround for Neoverse V2 erratum 2331132
Neoverse V2 erratum 2331132 is a Cat B erratum that applies to all
revisions <= r0p2 and is still open. The workaround is to write the
value 4'b1001 to the PF_MODE bits in the IMP_CPUECTLR2_EL1 register
which will place the data prefetcher in the most conservative mode
instead of disabling it.
SDEN documentation:
https://developer.arm.com/documentation/SDEN2332927/latest
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: Ic6c76375df465a4ad2e20dd7add7037477d973c1
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| e99df5c2 | 08-Sep-2023 |
Bipin Ravi <bipin.ravi@arm.com> |
Merge changes from topic "sm/errata_X3" into integration
* changes:
fix(cpus): workaround for Cortex-X3 erratum 2742421
feat(errata_abi): add support for Cortex-X3 |
| 5b0e4438 | 05-Sep-2023 |
Sona Mathew <sonarebecca.mathew@arm.com> |
fix(cpus): workaround for Cortex-X3 erratum 2742421
Cortex-X3 erratum 2742421 is a Cat B erratum that applies to
all revisions <= r1p1 and is fixed in r1p2. The workaround is to
set CPUACTLR5_EL1[56
fix(cpus): workaround for Cortex-X3 erratum 2742421
Cortex-X3 erratum 2742421 is a Cat B erratum that applies to
all revisions <= r1p1 and is fixed in r1p2. The workaround is to
set CPUACTLR5_EL1[56:55] to 2'b01.
SDEN documentation:
https://developer.arm.com/documentation/2055130/latest
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
Change-Id: Idadd323e419739fe909b9b68ea2dbe857846666b
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| 9c165216 | 06-Sep-2023 |
Sona Mathew <sonarebecca.mathew@arm.com> |
feat(errata_abi): add support for Cortex-X3
Add errata ABI support for Cortex-X3 CPU.
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
Change-Id: Ifb68178948860cafe25b351f20c480c847608a1b |
| 74bfe31f | 29-Aug-2023 |
Bipin Ravi <bipin.ravi@arm.com> |
fix(cpus): workaround for Neoverse N2 erratum 2009478
Neoverse N2 erratum 2009478 is a Cat B erratum that applies to
revision r0p0 and is fixed in r0p1. The workaround is to clear
the ED bit for all
fix(cpus): workaround for Neoverse N2 erratum 2009478
Neoverse N2 erratum 2009478 is a Cat B erratum that applies to
revision r0p0 and is fixed in r0p1. The workaround is to clear
the ED bit for all core error records before setting the PWRDN_EN
bit in CPUPWRCTLR_EL1 to request a power down.
SDEN documentation:
https://developer.arm.com/documentation/SDEN1982442/latest
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: Ic5ef58c9e795b90026af1d2b09edc0eea3ceee51
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| 4ede8c39 | 14-Aug-2023 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes from topic "el3_direct_msg" into integration
* changes:
docs(spm): document new build option
feat(fvp): spmd logical partition smc handler
feat(fvp): add spmd logical partition
Merge changes from topic "el3_direct_msg" into integration
* changes:
docs(spm): document new build option
feat(fvp): spmd logical partition smc handler
feat(fvp): add spmd logical partition
feat(spmd): get logical partitions info
feat(spmd): add partition info get regs
refactor(ff-a): move structure definitions
feat(spmd): el3 direct message API
feat(spmd): add spmd logical partitions
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| 5cf311f3 | 04-Mar-2023 |
Raghu Krishnamurthy <raghu.ncstate@gmail.com> |
feat(fvp): add spmd logical partition
This patch changes spmd.mk to include one or more SPMD logical
partitions specific to a platform. It also adds a basic SPMD logical
partition to fvp.
Change-Id
feat(fvp): add spmd logical partition
This patch changes spmd.mk to include one or more SPMD logical
partitions specific to a platform. It also adds a basic SPMD logical
partition to fvp.
Change-Id: I2075e0458c92813913b28cbf4cfffc1f151e65cf
Signed-off-by: Raghu Krishnamurthy <raghu.ncstate@gmail.com>
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| 95f7f6d8 | 23-Apr-2023 |
Raghu Krishnamurthy <raghu.ncstate@gmail.com> |
feat(spmd): get logical partitions info
This patch enables FF-A secure partitions and the SPMC to query EL3 SPMD
logical partitions that are present in the system via partition get info
regs abi. No
feat(spmd): get logical partitions info
This patch enables FF-A secure partitions and the SPMC to query EL3 SPMD
logical partitions that are present in the system via partition get info
regs abi. Note that normal world will not be able to see EL3 SPMD
logical partitions as per the spec.
Signed-off-by: Raghu Krishnamurthy <raghu.ncstate@gmail.com>
Change-Id: I3fca8aed8ae156a559a74521803324c13ae3d55a
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| 0b850e9e | 22-Apr-2023 |
Raghu Krishnamurthy <raghu.ncstate@gmail.com> |
feat(spmd): add partition info get regs
This patch adds support for an EL3 SPMD logical partition to discover
secure partitions using the FFA_PARTITION_INFO_GET_REGS abi. It also
adds helper functio
feat(spmd): add partition info get regs
This patch adds support for an EL3 SPMD logical partition to discover
secure partitions using the FFA_PARTITION_INFO_GET_REGS abi. It also
adds helper functions for a logical partition to use the information
returned in registers in a meaningful way.
Signed-off-by: Raghu Krishnamurthy <raghu.ncstate@gmail.com>
Change-Id: Id69488e7367e17e2dfa6c8e332be3c8d41f6c773
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| 5ca1619f | 22-Apr-2023 |
Raghu Krishnamurthy <raghu.ncstate@gmail.com> |
refactor(ff-a): move structure definitions
Move ffa_partition_info_get definitions from EL3 SPMC private header
files to common header files. The structures are common to FF-A and are
useful for the
refactor(ff-a): move structure definitions
Move ffa_partition_info_get definitions from EL3 SPMC private header
files to common header files. The structures are common to FF-A and are
useful for the EL3 SPMD logical partitions.
Signed-off-by: Raghu Krishnamurthy <raghu.ncstate@gmail.com>
Change-Id: I19de3f6cb3351afa873022da1397a475a84e3d8b
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| 66bdfd6e | 03-Mar-2023 |
Raghu Krishnamurthy <raghu.ncstate@gmail.com> |
feat(spmd): el3 direct message API
This patch implements an API that is exposed to SPMD logical partitions
that can be used to send direct messages to a secure partition.
It also adds required code
feat(spmd): el3 direct message API
This patch implements an API that is exposed to SPMD logical partitions
that can be used to send direct messages to a secure partition.
It also adds required code in the SPMD smc handler to complete the
direct response appropriately.
Change-Id: I2d0e38415f13ad4fd28f8984d565036b7d3a9e71
Signed-off-by: Raghu Krishnamurthy <raghu.ncstate@gmail.com>
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| 12d28067 | 17-Jul-2023 |
Arvind Ram Prakash <arvind.ramprakash@arm.com> |
fix(cpus): workaround for Neoverse N2 erratum 2779511
Neoverse N2 erratum 2779511 is a Cat B erratum that applies to
all revisions <=r0p2 and is fixed in r0p3. The workaround is to
set bit[47] of CP
fix(cpus): workaround for Neoverse N2 erratum 2779511
Neoverse N2 erratum 2779511 is a Cat B erratum that applies to
all revisions <=r0p2 and is fixed in r0p3. The workaround is to
set bit[47] of CPUACTLR3_EL1
SDEN documentation:
https://developer.arm.com/documentation/SDEN1982442/latest
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: Iaa0e30de8473ecb1df1fcca3a45904aac2e419b3
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| eb44035c | 05-Jul-2023 |
Arvind Ram Prakash <arvind.ramprakash@arm.com> |
fix(cpus): workaround for Neoverse N2 erratum 2743014
Neoverse N2 erratum 2743014 is a Cat B erratum that applies to
all revisions <=r0p2 and is fixed in r0p3. The workaround is to
set CPUACTLR5_EL1
fix(cpus): workaround for Neoverse N2 erratum 2743014
Neoverse N2 erratum 2743014 is a Cat B erratum that applies to
all revisions <=r0p2 and is fixed in r0p3. The workaround is to
set CPUACTLR5_EL1[56:55] to 2'b01.
SDEN documentation:
https://developer.arm.com/documentation/SDEN1982442/latest
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: Ie7e1be5dea9d1f74738f9fed0fb58bfd41763192
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| 890b5088 | 25-Feb-2023 |
Raghu Krishnamurthy <raghu.ncstate@gmail.com> |
feat(spmd): add spmd logical partitions
Add header file to help with creation of SPMD logical partitions. Also
update linker files to create sections to record SPMD logical partitions
declared. This
feat(spmd): add spmd logical partitions
Add header file to help with creation of SPMD logical partitions. Also
update linker files to create sections to record SPMD logical partitions
declared. This follows the same pattern as the EL3 SPMC's logical
partitions. This patch also adds initialization of SPMD logical
partitions when the SPMD comes up.
ENABLE_SPMD_LP is a build flag that is used to enable support for
SPMD logical partitions.
Note that the approach chosen is to keep SPMD and SPMC logical
partition support separate, as opposed to extend the existing SPMC
logical partition support since the code would need to have a number of
ifdefs and the interactions with various build options such as
SPMC_AT_EL3 needs to be accounted for, which would make code more
complicated.
Signed-off-by: Raghu Krishnamurthy <raghu.ncstate@gmail.com>
Change-Id: I9642ddbf6ea26dd3f4a283baec598d61c07e3661
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| abe80629 | 25-Jul-2023 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge "fix(el3-spmc): fix incorrect CASSERT" into integration |
| fbc90e0f | 25-Jul-2023 |
Bipin Ravi <bipin.ravi@arm.com> |
Merge "fix(cpus): workaround for Neoverse V2 erratum 2801372" into integration |
| 1dd79f9e | 12-Jun-2023 |
Demi Marie Obenour <demiobenour@gmail.com> |
fix(el3-spmc): fix incorrect CASSERT
Check that the size of desc->emad_count is 4, not that sizeof(int) is
nonzero. Also improve a comment.
Change-Id: I8bf69b637158ddffe2d08aed3d9879a4d7fd3514
Sig
fix(el3-spmc): fix incorrect CASSERT
Check that the size of desc->emad_count is 4, not that sizeof(int) is
nonzero. Also improve a comment.
Change-Id: I8bf69b637158ddffe2d08aed3d9879a4d7fd3514
Signed-off-by: Demi Marie Obenour <demiobenour@gmail.com>
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| ece8f7d7 | 13-Feb-2023 |
Boyan Karatotev <boyan.karatotev@arm.com> |
refactor(cm): set MDCR_EL3/CPTR_EL3 bits in respective feat_init_el3() only
These bits (MDCR_EL3.{NSTB, NSTBE, TTRF, TPM}, CPTR_EL3.TTA) only affect
EL2 (and lower) execution. Each feat_init_el3() i
refactor(cm): set MDCR_EL3/CPTR_EL3 bits in respective feat_init_el3() only
These bits (MDCR_EL3.{NSTB, NSTBE, TTRF, TPM}, CPTR_EL3.TTA) only affect
EL2 (and lower) execution. Each feat_init_el3() is called long before
any lower EL has had a chance to execute, so setting the bits at reset
is redundant. Removing them from reset code also improves readability of
the immutable EL3 state.
Preserve the original intention for the TTA bit of "enabled for NS and
disabled everywhere else" (inferred from commit messages d4582d3088 and
2031d6166a and the comment). This is because CPTR_EL3 will be contexted
and so everyone will eventually get whatever NS has anyway.
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I3d24b45d3ea80882c8e450b2d9db9d5531facec1
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| 40c81ed5 | 06-Jul-2023 |
Moritz Fischer <moritzf@google.com> |
fix(cpus): workaround for Neoverse V2 erratum 2801372
Neoverse V2 erratum 2801372 is a Cat B erratum that applies to
all revisions <=r0p1 and is fixed in r0p2. The workaround is to
insert a dsb befo
fix(cpus): workaround for Neoverse V2 erratum 2801372
Neoverse V2 erratum 2801372 is a Cat B erratum that applies to
all revisions <=r0p1 and is fixed in r0p2. The workaround is to
insert a dsb before the isb in the power down sequence.
This errata is explained in SDEN 2332927 available at:
https://developer.arm.com/documentation/SDEN2332927
Change-Id: I8716b9785a67270a72ae329dc49a2f2239dfabff
Signed-off-by: Moritz Fischer <moritzf@google.com>
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| 6c91fc44 | 12-Jul-2023 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
fix(spmd): perform G0 interrupt acknowledge and deactivation
Prior to delegating handling of Group0 secure interrupt to platform
handler, SPMD framework must acknowledge the highest pending interrup
fix(spmd): perform G0 interrupt acknowledge and deactivation
Prior to delegating handling of Group0 secure interrupt to platform
handler, SPMD framework must acknowledge the highest pending interrupt.
Moreover, once the platform has handled the interrupt successfully,
SPMD must deactivate the interrupt.
The rationale behind this decision is SPMD framework is well suited to
perform interrupt management at GIC boundary while the platform handler
is well equipped to deal with the device interface related to the
interrupt.
This patch also fixes a bug in the error code returned upon invocation
of FFA_EL3_INTR_HANDLE from normal world.
Change-Id: If8fef51899e25f966038cc01ec58c84ee25e88eb
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
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