feat(rmmd): el3 token sign during attestation

Add required SMCs by RMM to push attestation signing requests to EL3
and get responses. EL3 may then choose to push these requests to a HES
as suitable

feat(rmmd): el3 token sign during attestation

Add required SMCs by RMM to push attestation signing requests to EL3
and get responses. EL3 may then choose to push these requests to a HES
as suitable for a platform. This patch also supports the new
RMM_EL3_FEATURES interface, that RMM can use to query for support for
HES based signing. The new interface exposes a feature register with
different bits defining different discoverable features. This new
interface is available starting the 0.4 version of the RMM-EL3
interface, causing the version to bump up. This patch also adds a
platform port for FVP that implements the platform hooks required to
enable the new SMCs, but it does not push to a HES and instead copies a
zeroed buffer in EL3.

Change-Id: I69c110252835122a9533e71bdcce10b5f2a686b2
Signed-off-by: Raghu Krishnamurthy <raghupathyk@nvidia.com>

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fix(el3-spmc): use write_el1_ctx_timer() macro to set cntkctl_el1 value

commit 42e35d2f8c0e
("refactor(cm): convert el1 ctx assembly offset entries to c structure")
moves cntkctl_el1 register from e

fix(el3-spmc): use write_el1_ctx_timer() macro to set cntkctl_el1 value

commit 42e35d2f8c0e
("refactor(cm): convert el1 ctx assembly offset entries to c structure")
moves cntkctl_el1 register from el1_sysregs_t's common to arch_timer
structure.
To set cntkctl_el1, it should use write_el1_ctx_timer() instead of
write_el1_ctx_common() otherwise, build failed.

Signed-off-by: Levi Yun <yeoreum.yun@arm.com>
Change-Id: Ifa1ca6e056fa95bd07598d20705856e208670808

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fix(drtm): do cache maintenance before launching DLME

According to the specifications, the DLME launch should occur with
the cache disabled. Initially, the cache was enabled to enhance
performance.

fix(drtm): do cache maintenance before launching DLME

According to the specifications, the DLME launch should occur with
the cache disabled. Initially, the cache was enabled to enhance
performance. However, to comply with the PSCI specification, we
decided to disable it before launching the DLME.

Also, ensure that full DLME region is invalidated.

Change-Id: Idf619afb7e4a34ebe213bd3b559105ade993f3ad
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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Merge "refactor(rmmd): plat token requests in pieces" into integration

refactor(rmmd): plat token requests in pieces

Until now, the attestation token size was limited by the size of the
shared buffer between RMM and TF-A. With this change, RMM can now
request the token

refactor(rmmd): plat token requests in pieces

Until now, the attestation token size was limited by the size of the
shared buffer between RMM and TF-A. With this change, RMM can now
request the token in pieces, so they fit in the shared buffer. A new
output parameter was added to the SMC call, which will return (along
with the size of bytes copied into the buffer) the number of bytes
of the token that remain to be retrieved.

TF-A will keep an offset variable that will indicate the position in
the token where the next call will retrieve bytes from. This offset
will be increased on every call by adding the number number of bytes
copied. If the received hash size is not 0, TF-A will reset the
offset to 0 and copy from that position on.

The SMC call will now return at most the size of the shared buffer
in bytes on every call. Therefore, from now on, multiple SMC calls
may be needed to be issued if the token size exceeds the shared
buffer size.

Change-Id: I591f7013d06f64e98afaf9535dbea6f815799723
Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>

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fix(spmd): remove spmd_handle_spmc_message

The function `spmd_handle_spmc_message` was added into SPMD for
potential cases of SPMC sending a message (through SMC conduit)
to the SPMD. There is no lo

fix(spmd): remove spmd_handle_spmc_message

The function `spmd_handle_spmc_message` was added into SPMD for
potential cases of SPMC sending a message (through SMC conduit)
to the SPMD. There is no longer a use case for this scenario.

Instead, if such a message is received by SPMD, return FFA_ERROR.

Signed-off-by: Kathleen Capella <kathleen.capella@arm.com>
Change-Id: I74eda4cc0edf99c83a96d10981cf6d9e727207f8

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fix(drtm): return proper values for DRTM get and set error SMCs

The DRTM get and set error previously returned SMC_UNK when these
SMCs were issued. This has been corrected to return an appropriate
e

fix(drtm): return proper values for DRTM get and set error SMCs

The DRTM get and set error previously returned SMC_UNK when these
SMCs were issued. This has been corrected to return an appropriate
error code on failure, and success otherwise.
Also,align the error code values with the specification.

Change-Id: I8f11f94f1ab097245003dbde97365fa54e0097ba
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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fix(sdei): fix a crash when attempting to bind more events than are available

You can only bind a limited number of events in each range. If you
attempt to bind more, it was crashing. This patch mak

fix(sdei): fix a crash when attempting to bind more events than are available

You can only bind a limited number of events in each range. If you
attempt to bind more, it was crashing. This patch makes it return an
error code instead.

Change-Id: Ib19f0f0780959ded244d45349d9d6c8607255c15
Signed-off-by: Charlie Bareham <charlie.bareham@arm.com>

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chore(cm): reorganise sctlr_el1 and tcr_el1 ctx code

SCTLR_EL1 and TCR_EL1 regs are included either as part of errata
"ERRATA_SPECULATIVE_AT" or under el1_sysregs_t context structure.
The code to wr

chore(cm): reorganise sctlr_el1 and tcr_el1 ctx code

SCTLR_EL1 and TCR_EL1 regs are included either as part of errata
"ERRATA_SPECULATIVE_AT" or under el1_sysregs_t context structure.
The code to write and read into these context entries, looks
repetitive and is invoked at most places.
This section is refactored to bring them under a static procedure,
keeping the code neat and easier to maintain.

Change-Id: Ib0d8c51bee09e1600c5baaa7f9745083dca9fee1
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>

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Merge changes from topic "mp/simd_ctxt_mgmt" into integration

* changes:
feat(fvp): allow SIMD context to be put in TZC DRAM
docs(simd): introduce CTX_INCLUDE_SVE_REGS build flag
feat(fvp): ad

Merge changes from topic "mp/simd_ctxt_mgmt" into integration

* changes:
feat(fvp): allow SIMD context to be put in TZC DRAM
docs(simd): introduce CTX_INCLUDE_SVE_REGS build flag
feat(fvp): add Cactus partition manifest for EL3 SPMC
chore(simd): remove unused macros and utilities for FP
feat(el3-spmc): support simd context management upon world switch
feat(trusty): switch to simd_ctx_save/restore apis
feat(pncd): switch to simd_ctx_save/restore apis
feat(spm-mm): switch to simd_ctx_save/restore APIs
feat(simd): add rules to rationalize simd ctxt mgmt
feat(simd): introduce simd context helper APIs
feat(simd): add routines to save, restore sve state
feat(simd): add sve state to simd ctxt struct
feat(simd): add data struct for simd ctxt management

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feat(el3-spmc): support simd context management upon world switch

This patch performs necessary simd context management operations for
context switch from NWd to SWD and vice versa.

Change-Id: Ife0

feat(el3-spmc): support simd context management upon world switch

This patch performs necessary simd context management operations for
context switch from NWd to SWD and vice versa.

Change-Id: Ife01fffc4e2a7f3deb9b6273424161c225fdbbfb
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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feat(spm-mm): switch to simd_ctx_save/restore APIs

This patch demonstrates the trivial changes to transparently switch
the fpregs_context_* helpers to simd_ctx_* helpers.

Signed-off-by: Madhukar Pa

feat(spm-mm): switch to simd_ctx_save/restore APIs

This patch demonstrates the trivial changes to transparently switch
the fpregs_context_* helpers to simd_ctx_* helpers.

Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
Signed-off-by: Okash Khawaja <okash@google.com>
Change-Id: I14bda6bd0ead1f34a570b59be8dec3ac40891c20

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refactor(errata-abi): move EXTRACT_PARTNUM to arch.h

This patch moves EXTRACT_PARTNUM from errata abi includes
to arch.h which is part of common includes

Change-Id: Id8bbaf21566f3145a75cfa0dafec682

refactor(errata-abi): move EXTRACT_PARTNUM to arch.h

This patch moves EXTRACT_PARTNUM from errata abi includes
to arch.h which is part of common includes

Change-Id: Id8bbaf21566f3145a75cfa0dafec6823ed2df3a9
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>

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Merge changes from topic "jc/refact_el1_ctx" into integration

* changes:
refactor(cm): convert el1-ctx assembly offset entries to c structure
feat(cm): add explicit context entries for ERRATA_SP

Merge changes from topic "jc/refact_el1_ctx" into integration

* changes:
refactor(cm): convert el1-ctx assembly offset entries to c structure
feat(cm): add explicit context entries for ERRATA_SPECULATIVE_AT

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refactor(cm): convert el1-ctx assembly offset entries to c structure

Currently the EL1 part of the context structure (el1_sysregs_t),
is coupled with feature flags reducing the context memory alloca

refactor(cm): convert el1-ctx assembly offset entries to c structure

Currently the EL1 part of the context structure (el1_sysregs_t),
is coupled with feature flags reducing the context memory allocation
for platforms, that don't enable/support all the architectural
features at once.

Similar to the el2 context optimization commit-"d6af234" this patch
further improves this section by converting the assembly context-offset
entries into a c structure. It relies on garbage collection of the
linker removing unreferenced structures from memory, as well as aiding
in readability and future maintenance. Additionally, it eliminates
the #ifs usage in 'context_mgmt.c' source file.

Change-Id: If6075931cec994bc89231241337eccc7042c5ede
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>

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feat(cm): add explicit context entries for ERRATA_SPECULATIVE_AT

* Currently, "ERRATA_SPECUALTIVE_AT" errata is enabled by default
for few cores and they need context entries for saving and
rest

feat(cm): add explicit context entries for ERRATA_SPECULATIVE_AT

* Currently, "ERRATA_SPECUALTIVE_AT" errata is enabled by default
for few cores and they need context entries for saving and
restoring EL1 regs "SCTLR_EL1 and TCR_EL1" registers at all times.

* This prevents the mechanism of decoupling EL1 and EL2 registers,
as EL3 firmware shouldn't be handling both simultaneously.

* Depending on the build configuration either EL1 or EL2 context
structures need to included, which would result in saving a good
amount of context memory.

* In order to achieve this it's essential to have explicit context
entries for registers supporting "ERRATA_SPECULATIVE_AT".

* This patch adds two context entries under "errata_speculative_at"
structure to assist this errata and thereby allows decoupling
EL1 and EL2 context structures.

Change-Id: Ia50626eea8fb64899a2e2d81622adbe07fe77d65
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>

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fix(rmmd): remove the assert check for RMM_BASE

This patch removes the assert from rmmd_setup() that checks if the
RMM image PC is equal to RMM_BASE. The RMM image can be relocated to
any address in

fix(rmmd): remove the assert check for RMM_BASE

This patch removes the assert from rmmd_setup() that checks if the
RMM image PC is equal to RMM_BASE. The RMM image can be relocated to
any address in the DRAM by the previous bootloader. So, providing the
RMM base address at compile time is not feasible for such platforms.

The assert check is now replaced with a runtime check for the RMM image.

Change-Id: I568cdb6f76f41d0dcdc7a95feb75e252a7c5c930
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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fix(std_svc): continue boot if rmmd_setup fails

This patch allows the boot sequence to continue even if
rmmd_setup() fails. This allows platforms to use the same
RME-enabled image to support the sce

fix(std_svc): continue boot if rmmd_setup fails

This patch allows the boot sequence to continue even if
rmmd_setup() fails. This allows platforms to use the same
RME-enabled image to support the scenarios where RMM image
is not present.

Change-Id: Ie4de15fb98ae7226eda410e15f1a650108dd8fb3
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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fix(rmmd): ignore SMC FID when RMM image is not present

This patch marks the RMM boot as failed, to ignore the SMC
FID for the RMM at runtime, if RMM image is not present on
the platform.

Change-Id

fix(rmmd): ignore SMC FID when RMM image is not present

This patch marks the RMM boot as failed, to ignore the SMC
FID for the RMM at runtime, if RMM image is not present on
the platform.

Change-Id: I3c19d886d32c56837a1a0d260d5204da8b2d12f1
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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fix(rmmd): fail gracefully if RME is not enabled

This patch converts the assert check for RME presence into
a runtime check and returns an error to fail gracefully. This
allows platforms to use the

fix(rmmd): fail gracefully if RME is not enabled

This patch converts the assert check for RME presence into
a runtime check and returns an error to fail gracefully. This
allows platforms to use the same image on boards that do not
support RME too.

Change-Id: I0cacdd7afd85ed3581e90ea81f0a51d076adb875
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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fix(rmmd): handle RMMD manifest loading failure

This patch sets the rmm_boot_failed flag to true if the RMMD
manifest loading fails. This instructs the RMMD to ignore all
SMC FID for the RMM at runt

fix(rmmd): handle RMMD manifest loading failure

This patch sets the rmm_boot_failed flag to true if the RMMD
manifest loading fails. This instructs the RMMD to ignore all
SMC FID for the RMM at runtime.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: If61be6200e28fcea7a5ad697393e83679f488abc

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refactor(spmd): move plat_my_core_pos calls

By tracing instruction execution, it is observed:
Placing plat_my_core_pos at top of functions translate by the compiler
into calling those functions even

refactor(spmd): move plat_my_core_pos calls

By tracing instruction execution, it is observed:
Placing plat_my_core_pos at top of functions translate by the compiler
into calling those functions even if the result is not consumed when not
printed.
plat_my_core_pos is used to retrieve the core id for the currently
running core, but effectively call sites are only consuming it for
verbosity purposes. Move plat_my_core_pos calls into the print functions
that require it.

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: Ia3549453b5e4de7c575a8887a4d19e318658d03e

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refactor(spmd): call cm_get_context once

As observed by tracing instruction execution the SMC_RET18
macro in spmd_smc_switch_state calls cm_get_context, however the
compiler expands it to multiple i

refactor(spmd): call cm_get_context once

As observed by tracing instruction execution the SMC_RET18
macro in spmd_smc_switch_state calls cm_get_context, however the
compiler expands it to multiple individual non-inlined calls to
this same function. Store the result of cm_get_context into a local
variable and use it in the macro such that this function is only called
once.

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: Ib4fa63aced2f07c67c057f54fef3780c85e91df7

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refactor(spmd): remove spmd_get_context_by_mpidr

spmd_get_context_by_mpidr calls plat_core_pos_by_mpidr defined in
platform's fvp_topology. This involves a lot of intricated inner calls
including ac

refactor(spmd): remove spmd_get_context_by_mpidr

spmd_get_context_by_mpidr calls plat_core_pos_by_mpidr defined in
platform's fvp_topology. This involves a lot of intricated inner calls
including access to power controller (taking/releasing a bakery lock).
Remove dependency from this function, and use plat_my_core_pos instead.

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I8e91858922e339de51056dba8803db74c8fd7420

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chore(errata-abi): minor variable rename

'cpu_partnumber' variable part of 'em_cpu_list' actually contains the
cpu midr value and not the actual part number. The part number is
extracted from midr v

chore(errata-abi): minor variable rename

'cpu_partnumber' variable part of 'em_cpu_list' actually contains the
cpu midr value and not the actual part number. The part number is
extracted from midr value in 'non_arm_interconnect_errata' function.

So 'cpu_partnumber' is misleading and the actual value is midr, thus
rename it to 'cpu_midr'.

Change-Id: I4bfe71ce24542d508e2bcf39a1097724d14c4511
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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