fix(mt8196): remove EC_SUSPEND_PIN initial setting

Move EC_SUSPEND_PIN (GPIO_AP_SUSPEND_L) init to coreboot and remove
EC_SUSPEND_PIN init from TF-A.

Signed-off-by: Wenzhen Yu <wenzhen.yu@mediatek.

fix(mt8196): remove EC_SUSPEND_PIN initial setting

Move EC_SUSPEND_PIN (GPIO_AP_SUSPEND_L) init to coreboot and remove
EC_SUSPEND_PIN init from TF-A.

Signed-off-by: Wenzhen Yu <wenzhen.yu@mediatek.com>
Change-Id: I3d7a5a923dc9f692495d99255427a39ef5852bf8

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fix(mt8196): remove SPM support for ES chip

We no longer maintain the device equipped with ES chip. Remove SPM
support for ES ship.

Signed-off-by: Wenzhen Yu <wenzhen.yu@mediatek.com>
Change-Id: I5

fix(mt8196): remove SPM support for ES chip

We no longer maintain the device equipped with ES chip. Remove SPM
support for ES ship.

Signed-off-by: Wenzhen Yu <wenzhen.yu@mediatek.com>
Change-Id: I5b2d035ec384a9861239f33dbe6df54c17f1285c

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feat(spm_mm): move mm_communication header define to general header

To support TPM start method with SIP, SIP handler dispatch request to
secure partition via MM_COMMUNICATE abi.
That means spm_mm s

feat(spm_mm): move mm_communication header define to general header

To support TPM start method with SIP, SIP handler dispatch request to
secure partition via MM_COMMUNICATE abi.
That means spm_mm sip handler should generate mm communication header.

Move mm_communication header's definition to spm_mm_svc header.

Change-Id: I40567c16e67b068ee83a39eff050d6578aecfb2c
Signed-off-by: Levi Yun <yeoreum.yun@arm.com>

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Merge "feat(mt8196): disable debug flag in APU driver" into integration

Merge changes I32bd0c71,I167e7398 into integration

* changes:
fix(arm): don't race on the build directory
fix(armada): don't race on the UART_IMAGE

feat(rockchip): update uart baudrate for rk3399

Set the UART baudrate to 1500000 since that is what the ROM code and
other components use. This reverts the change of baudrate in the commit
0c05748bd

feat(rockchip): update uart baudrate for rk3399

Set the UART baudrate to 1500000 since that is what the ROM code and
other components use. This reverts the change of baudrate in the commit
0c05748bdebf ("rockchip: fixes for the required") and enables logging
from BL31 and OP-TEE during boot and after the kernel has booted.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Change-Id: I5b5db25b069f3676ebb9dba2fa778601e05f1334

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Merge changes from topic "memory_bank" into integration

* changes:
fix(qemu): statically allocate bitlocks array
feat(qemu): update for renamed struct memory_bank
feat(fvp): increase GPT PPS t

Merge changes from topic "memory_bank" into integration

* changes:
fix(qemu): statically allocate bitlocks array
feat(qemu): update for renamed struct memory_bank
feat(fvp): increase GPT PPS to 1TB
feat(gpt): statically allocate bitlocks array
chore(gpt): define PPS in platform header files
feat(fvp): allocate L0 GPT at the top of SRAM
feat(fvp): change size of PCIe memory region 2
feat(rmm): add PCIe IO info to Boot manifest
feat(fvp): define single Root region

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refactor(arm): switch to rse_mbx_init

The rse_comms_init() function will be removed. The new function to use
is rse_mbx_init() for the MHU mailbox initialization.

Change-Id: I1932500ef71b6e895f0ee1

refactor(arm): switch to rse_mbx_init

The rse_comms_init() function will be removed. The new function to use
is rse_mbx_init() for the MHU mailbox initialization.

Change-Id: I1932500ef71b6e895f0ee164ee9c2b58becf4409
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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refactor(tc): add plat_rse_comms_init

The same way it is done for neoverse_rd, create a plat_rse_comms_init()
function to call rse_comms_init().

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Ch

refactor(tc): add plat_rse_comms_init

The same way it is done for neoverse_rd, create a plat_rse_comms_init()
function to call rse_comms_init().

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I12f3b8a38a5369decb4b97f8aceeb0dc81cbea28

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refactor(arm)!: rename PLAT_MHU_VERSION flag

In order to support a platform without MHU in RSE, update the flag
PLAT_MHU_VERSION. It is renamed PLAT_MHU and can take the following
entries: NO_MHU, M

refactor(arm)!: rename PLAT_MHU_VERSION flag

In order to support a platform without MHU in RSE, update the flag
PLAT_MHU_VERSION. It is renamed PLAT_MHU and can take the following
entries: NO_MHU, MHUv1, MHUv2, MHUv3...

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: Ia72e590088ce62ba8c9009f341b6135926947bee

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Merge changes from topic "imx8mq_build_fix" into integration

* changes:
fix(imx8m): fix imx8mq build break
fix(imx8mq): fix imx8mq build break due to hab

Merge "fix(altera): add in support for agilex5 b0 jtag id" into integration

feat(mt8196): disable debug flag in APU driver

Disable the debug flag from the driver to reduce debugging messages.

Change-Id: I9444f64acbf684debab56d8226b14c6c01200ea4
Signed-off-by: Gavin Liu <ga

feat(mt8196): disable debug flag in APU driver

Disable the debug flag from the driver to reduce debugging messages.

Change-Id: I9444f64acbf684debab56d8226b14c6c01200ea4
Signed-off-by: Gavin Liu <gavin.liu@mediatek.com>

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fix(arm): don't race on the build directory

Wait for it to have been created. This is the same issue as
commit db69d118294f08aae86378c98aa082ac73e15b73.

Change-Id: I32bd0c713e2837563d32131fb0beddb5

fix(arm): don't race on the build directory

Wait for it to have been created. This is the same issue as
commit db69d118294f08aae86378c98aa082ac73e15b73.

Change-Id: I32bd0c713e2837563d32131fb0beddb5533c0792
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(armada): don't race on the UART_IMAGE

UART_IMAGE is not set when WTP isn't. The error rules will then provide
a recipe for $(BUILD_PLAT). When building with a lot of cores (64) this
rule might b

fix(armada): don't race on the UART_IMAGE

UART_IMAGE is not set when WTP isn't. The error rules will then provide
a recipe for $(BUILD_PLAT). When building with a lot of cores (64) this
rule might be called before the directory is made, causing a build
failure.

Hoist the definition so that the depended path is correct.

Change-Id: I167e7398e576e667d0c5c1fc0f07ab8c8ef939a8
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge changes I765a7fa0,Ic33f0b6d,I8d1a88c7,I381f96be,I698fa849, ... into integration

* changes:
fix(cpus): clear CPUPWRCTLR_EL1.CORE_PWRDN_EN_BIT on reset
chore(docs): drop the "wfi" from `pwr_

Merge changes I765a7fa0,Ic33f0b6d,I8d1a88c7,I381f96be,I698fa849, ... into integration

* changes:
fix(cpus): clear CPUPWRCTLR_EL1.CORE_PWRDN_EN_BIT on reset
chore(docs): drop the "wfi" from `pwr_domain_pwr_down_wfi`
chore(psci): drop skip_wfi variable
feat(arm): convert arm platforms to expect a wakeup
fix(cpus): avoid SME related loss of context on powerdown
feat(psci): allow cores to wake up from powerdown
refactor: panic after calling psci_power_down_wfi()
refactor(cpus): undo errata mitigations
feat(cpus): add sysreg_bit_toggle

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fix(qemu): statically allocate bitlocks array

gpt_runtime_init() now takes the bitlock array's address and size as
argument. Rather than reserving space at the end of the L0 GPT for
storing bitlocks

fix(qemu): statically allocate bitlocks array

gpt_runtime_init() now takes the bitlock array's address and size as
argument. Rather than reserving space at the end of the L0 GPT for
storing bitlocks, allocate a static array and pass its address to
gpt_runtime_init(). This frees up a little bit of space formerly
reserved for alignment of the GPT.

Change-Id: I48a1a2bc230f64e13e3ed08b18ebdc2d387d77d0
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>

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feat(qemu): update for renamed struct memory_bank

The struct ns_dram_bank has been renamed to struct memory_bank, so
update plat/qemu accordingly.

Signed-off-by: Jens Wiklander <jens.wiklander@lina

feat(qemu): update for renamed struct memory_bank

The struct ns_dram_bank has been renamed to struct memory_bank, so
update plat/qemu accordingly.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Change-Id: If5ed92edd132c977009a7371ec53eca0ee35ef00

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feat(fvp): increase GPT PPS to 1TB

- Increase PPS for FVP from 64GB to 1TB.
- GPT L0 table for 1TB PPS requires 8KB memory.
- Set FVP_TRUSTED_SRAM_SIZE to 384 with ENABLE_RME=1
option.
- Add 256MB

feat(fvp): increase GPT PPS to 1TB

- Increase PPS for FVP from 64GB to 1TB.
- GPT L0 table for 1TB PPS requires 8KB memory.
- Set FVP_TRUSTED_SRAM_SIZE to 384 with ENABLE_RME=1
option.
- Add 256MB of PCIe memory region 1 and 3GB of
PCIe memory region 2 to FVP PAS regions array.

Change-Id: Icadd528576f53c55b5d461ff4dcd357429ba622a
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>

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feat(gpt): statically allocate bitlocks array

Statically allocate 'gpt_bitlock' array of fine-grained
'bitlock_t' data structures in arm_bl31_setup.c.
The amount of memory needed for this array is c

feat(gpt): statically allocate bitlocks array

Statically allocate 'gpt_bitlock' array of fine-grained
'bitlock_t' data structures in arm_bl31_setup.c.
The amount of memory needed for this array is controlled
by 'RME_GPT_BITLOCK_BLOCK' build option and 'PLAT_ARM_PPS'
macro defined in platform_def.h which specifies the size
of protected physical address space in bytes.
'PLAT_ARM_PPS' takes values from 4GB to 4PB supported by
Arm architecture.

Change-Id: Icf620b5039e45df6828d58fca089cad83b0bc669
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>

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chore(gpt): define PPS in platform header files

Define protected physical address size in bytes
PLAT_ARM_PPS macro for FVP and RDV3 in platform_def.h
files.

Change-Id: I7f6529dfbb8df864091fbefc0813

chore(gpt): define PPS in platform header files

Define protected physical address size in bytes
PLAT_ARM_PPS macro for FVP and RDV3 in platform_def.h
files.

Change-Id: I7f6529dfbb8df864091fbefc08131a0e6d689eb6
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>

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feat(fvp): allocate L0 GPT at the top of SRAM

This patch allocates level 0 GPT at the top of SRAM
for FVP. This helps to meet L0 GPT alignment requirements
and prevent the occurrence of possible unu

feat(fvp): allocate L0 GPT at the top of SRAM

This patch allocates level 0 GPT at the top of SRAM
for FVP. This helps to meet L0 GPT alignment requirements
and prevent the occurrence of possible unused gaps in SRAM.
Load addresses for FVP TB_FW, SOC_FW and TOS_FW DTBs are
defined in fvp_fw_config.dts via ARM_BL_RAM_BASE macro.

Change-Id: Iaa52e302373779d9fdbaf4e1ba40c10aa8d1f8bd
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>

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feat(rmm): add PCIe IO info to Boot manifest

- Add PCIe and SMMUv3 related information to DTS for
configurations with ENABLE_RME=1.
- Add entries for PCIe IO memory regions to Boot manifest
- Upda

feat(rmm): add PCIe IO info to Boot manifest

- Add PCIe and SMMUv3 related information to DTS for
configurations with ENABLE_RME=1.
- Add entries for PCIe IO memory regions to Boot manifest
- Update RMMD_MANIFEST_VERSION_MINOR from 3 to 4.
- Read PCIe related information from DTB and write it to
Boot manifest.
- Rename structures that used to describe DRAM layout
and now describe both DRAM and PCIe IO memory regions:
- ns_dram_bank -> memory_bank
- ns_dram_info -> memory_info.

Change-Id: Ib75d1af86076f724f5c330074e231f1c2ba8e21d
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>

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feat(fvp): define single Root region

For FVP model define single Root PAS which
includes EL3 DRAM data, L1 GPTs and SCP TZC.
This allows to decrease the number of PAS
regions passed to GPT library a

feat(fvp): define single Root region

For FVP model define single Root PAS which
includes EL3 DRAM data, L1 GPTs and SCP TZC.
This allows to decrease the number of PAS
regions passed to GPT library and use GPT
mapping with Contiguous descriptor of
larger block size.

Change-Id: I70f6babaebc14e5e0bce033783ec423c8a26c542
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>

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Merge "fix(mt8196): fix wrong register offset of dptx on MT8196" into integration