feat(mt8196): add Mediatek MMinfra stub implementation

Implement stub functions for the MMinfra (Multimedia Infrastructure)
driver to ensure that the build can pass when a prebuilt library is
not av

feat(mt8196): add Mediatek MMinfra stub implementation

Implement stub functions for the MMinfra (Multimedia Infrastructure)
driver to ensure that the build can pass when a prebuilt library is
not available.

Change-Id: Iadac654950c868d3743b13a1d6f7ab5d1015fb86
Signed-off-by: Yong Wu <yong.wu@mediatek.com>

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feat(mt8196): enable cirq for MediaTek MT8196

- Add CIRQ related information.

Signed-off-by: ot_chhao.chang <ot_chhao.chang@mediatek.com>
Change-Id: I758e933f9d53f7bfb16e3d7feb1c7f53516b1da6

Merge "feat(mediatek): add gic driver" into integration

Merge "refactor(mediatek): refactor the data type of the return value" into integration

Merge "fix(tc): fix compilation error" into integration

Merge "fix(xilinx): remove unused write_icc_asgi1r_el1()" into integration

fix(xilinx): remove unused write_icc_asgi1r_el1()

The commit 427e46ddea1e ("fix(xilinx): fix sending sgi to linux")
removed code which called write_icc_asgi1r_el1() but function itself
wasn't remove

fix(xilinx): remove unused write_icc_asgi1r_el1()

The commit 427e46ddea1e ("fix(xilinx): fix sending sgi to linux")
removed code which called write_icc_asgi1r_el1() but function itself
wasn't removed.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: I95a1424b0546f3f4a5e4611de34441b96e70b7d3

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fix(tc): fix compilation error

When the SPD_spmd configuration is disabled, the compiler complaints:

plat/arm/board/tc/tc_bl2_dpe.c:234:22: error: unused variable 'array_size' [-Werror=unused-varia

fix(tc): fix compilation error

When the SPD_spmd configuration is disabled, the compiler complaints:

plat/arm/board/tc/tc_bl2_dpe.c:234:22: error: unused variable 'array_size' [-Werror=unused-variable]
234 | const size_t array_size = ARRAY_SIZE(tc_dpe_metadata);
| ^~~~~~~~~~
plat/arm/board/tc/tc_bl2_dpe.c:233:16: error: unused variable 'i' [-Werror=unused-variable]
233 | size_t i;
| ^
cc1: all warnings being treated as errors

Move variable declarations into the code chunk protected by the SPD_spmd
configuration.

Change-Id: I1a3889938e2d4ec5efec516e9ef54034f9d711b2
Signed-off-by: Leo Yan <leo.yan@arm.com>

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Merge changes I3f63d597,I40fc21f5 into integration

* changes:
feat(mt8196): add mtcmos driver
feat(mt8196): add DCM driver

Merge changes I1126311e,I6ae5b5b4,I1b907256,I9facb6bf,Ie51cffeb, ... into integration

* changes:
feat(mt8196): add vcore dvfs drivers
feat(mt8196): add LPM v2 support
feat(mt8196): add SPM com

Merge changes I1126311e,I6ae5b5b4,I1b907256,I9facb6bf,Ie51cffeb, ... into integration

* changes:
feat(mt8196): add vcore dvfs drivers
feat(mt8196): add LPM v2 support
feat(mt8196): add SPM common version support
feat(mt8196): add SPM common driver support
feat(mt8196): add SPM basic features support
feat(mt8196): add SPM features support
feat(mt8196): enable PMIC low power setting
feat(mt8196): add mcdi driver
feat(mt8196): add pwr_ctrl module for CPU power management
feat(mt8196): add mcusys moudles for power management
feat(mt8196): add CPC module for power management
feat(mt8196): add topology module for power management
feat(mt8196): add SPMI driver
feat(mt8196): add PMIC driver

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feat(mt8196): add mtcmos driver

add mtcmos driver for ufs power control

Signed-off-by: Guangjie Song <guangjie.song@mediatek.com>
Change-Id: I3f63d5976906aaca91a71a147497e9345339774d

feat(mt8196): add DCM driver

DCM means dynamic clock management, and it can dynamically slow down
or gate clocks during CPU or bus idle.

Add MCUSYS or bus related DCM drivers.
Enable MCUSYS or bus

feat(mt8196): add DCM driver

DCM means dynamic clock management, and it can dynamically slow down
or gate clocks during CPU or bus idle.

Add MCUSYS or bus related DCM drivers.
Enable MCUSYS or bus related DCM by default.

Signed-off-by: Guangjie Song <guangjie.song@mediatek.com>
Change-Id: I40fc21f5808962ca46870a2f3b9963dc8088f877

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Merge "fix(rdv3): fix comment for DRAM1 carveout size" into integration

Merge changes from topic "upstream_sp_num" into integration

* changes:
fix(tc): enable certificate on the last secure partition
feat(sptool): populate secure partition number in makefile

fix(tc): enable certificate on the last secure partition

Distros (e.g. Buildroot and Android) can have different secure partition
layout.

This commit iterates the DPE metadata table and finds index

fix(tc): enable certificate on the last secure partition

Distros (e.g. Buildroot and Android) can have different secure partition
layout.

This commit iterates the DPE metadata table and finds index (i) for the
first entry of the secure partition, connecting with the defined secure
partition number NUM_SP, so the last secure partition index is:

i + NUM_SP - 1

Instead of setting the certificate in hard code, dynamically enables the
certificate for the last secure partition base on calculated index.

Signed-off-by: Ben Horgan <ben.horgan@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
Change-Id: Idd11b4f463bf5ccc8d82cd06bd21deeebbda67d9

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fix(stm32mp2): correct early/crash console init

The previous code used 64-bit registers as the target and source for
load and store operations on 32-bit hardware registers. In certain
cases (e.g., w

fix(stm32mp2): correct early/crash console init

The previous code used 64-bit registers as the target and source for
load and store operations on 32-bit hardware registers. In certain
cases (e.g., when using USART1 as the debug console), this could result
in deadlocks where the A35 gets stuck in a permanent loop due to test
conditions that are never fulfilled.

To resolve this issue, 32-bit registers are now used for these
operations.

Change-Id: Id2c03a1df26738fe815079da042cc2dd989f4f8e
Signed-off-by: Boerge Struempfel <boerge.struempfel@gmail.com>

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fix(rdv3): fix comment for DRAM1 carveout size

Corrected the comment for the size of NRD_CSS_DRAM1_CARVEOUT_SIZE
(0x0C000000) from 117MB to 192MB

Signed-off-by: Rakshit Goyal <rakshit.goyal@arm.com

fix(rdv3): fix comment for DRAM1 carveout size

Corrected the comment for the size of NRD_CSS_DRAM1_CARVEOUT_SIZE
(0x0C000000) from 117MB to 192MB

Signed-off-by: Rakshit Goyal <rakshit.goyal@arm.com>
Change-Id: I289d37f50e70b936f717d4579d73882fac28ee95

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Merge changes Ided750de,Id3cc887c into integration

* changes:
docs(gxl): add build instructions for booting BL31 from U-Boot SPL
feat(gxl): add support for booting from U-Boot SPL/with standard

Merge changes Ided750de,Id3cc887c into integration

* changes:
docs(gxl): add build instructions for booting BL31 from U-Boot SPL
feat(gxl): add support for booting from U-Boot SPL/with standard params

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feat(versal2): update platform version to versal2

Extend board detection with saving information about PS,
PMC and RTL versions. Variables can be use to cover
different behavior based on version and

feat(versal2): update platform version to versal2

Extend board detection with saving information about PS,
PMC and RTL versions. Variables can be use to cover
different behavior based on version and version
information is also printed for chip identification.

Change-Id: Ia37418f6a31426a5763fb89fc76fef91d09df155
Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>

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fix(tc): enable Last-level cache (LLC) for tc4

EXTLLC bit in CPUECTLR_EL1(for non-gelas cpus) and in CPUECTLR2_EL1
register for gelas cpu enables external Last-level cache in the system,

External L

fix(tc): enable Last-level cache (LLC) for tc4

EXTLLC bit in CPUECTLR_EL1(for non-gelas cpus) and in CPUECTLR2_EL1
register for gelas cpu enables external Last-level cache in the system,

External LLC is present on TC4 systems in MCN but it is not enabled in
CPU registers so enable it.

On TC4, Gelas vs Non-Gelas CPUs have different bits to enable EXTLLC
so take care of that as well.

Change-Id: Ic6a74b4af110a3c34d19131676e51901ea2bf6e3
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen.Zeyada <Icen.Zeyada2@arm.com>

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fix(rdn2): add LCA multichip data for RD-N2-Cfg2

This patch adds the routing table addresses required for LCA
enablement on RD-N2-Cfg2. CMN on RD-N2-Cfg2 uses AXI Stream IDs
to route LCA connections

fix(rdn2): add LCA multichip data for RD-N2-Cfg2

This patch adds the routing table addresses required for LCA
enablement on RD-N2-Cfg2. CMN on RD-N2-Cfg2 uses AXI Stream IDs
to route LCA connections to the correct downstream tx_cxs_a4s
port. The data programmed in the routing table are the A4S IDs
of each chip.

Change-Id: I46e558f3be7f0d51b768b7c5586f15e6bc517f3a
Signed-off-by: Jerry Wang <Jerry.Wang4@arm.com>

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fix(rdv3): add LCA multichip data for RD-V3-Cfg2

This patch adds the routing table addresses required for LCA
enablement on RD-V3-Cfg2. Since LCA connection on rdv3 uses ACE5L
instead of A4S, the ad

fix(rdv3): add LCA multichip data for RD-V3-Cfg2

This patch adds the routing table addresses required for LCA
enablement on RD-V3-Cfg2. Since LCA connection on rdv3 uses ACE5L
instead of A4S, the addresses programmed in the routing table is
the address of memory mapped HNI with chip offset.

Change-Id: Ic235983d63e8ab3492ae566b68841d0659724e45
Signed-off-by: Jerry Wang <Jerry.Wang4@arm.com>

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feat(gic): add support for local chip addressing

This patch adds support for Local Chip Addressing (LCA). In a multi-chip
system, enablig LCA allows each GIC Distributor to maintain its own
version

feat(gic): add support for local chip addressing

This patch adds support for Local Chip Addressing (LCA). In a multi-chip
system, enablig LCA allows each GIC Distributor to maintain its own
version of routing table. This feature is activated when the
GICD_CFGID.LCA bit is set to 1.

The existing `gic600_multichip_data` data structure did not account for
the LCA feature. To support LCA:
- `rt_owner_base` is replaced by `base_addrs[]`. This is required
because each GICD in the system needs to be configured independently,
and their base addresses must be passed to the driver.
- `chip_addrs` is changed from 1D to 2D array to store the routing table
for each chip's GICD. The entries in `chip_addrs` are configuration
dependent, as the GIC specification does not enforce this.

On a multi-chip platform with chip count N where LCA is enabled by
default, the `gic600_multichip_data` structure should contain all copies
of the routing table (N*N entries). On platforms where LCA is not
supported, only the first sub-array with N entries is required. The
function signature of `gic600_multichip_init` remains unchanged, but if
the LCA feature is enabled, the driver will expect the routing table
configuration in the described format.

Change-Id: I8830c2cf90db6a0cae78e99914cd32c637284a2b
Signed-off-by: Jerry Wang <Jerry.Wang4@arm.com>

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Merge changes from topic "xlnx_fix_plat_single_ret" into integration

* changes:
fix(versal2): modify function to have single return
fix(versal-net): modify function to have single return
fix(v

Merge changes from topic "xlnx_fix_plat_single_ret" into integration

* changes:
fix(versal2): modify function to have single return
fix(versal-net): modify function to have single return
fix(versal): modify function to have single return
fix(xilinx): modify function to have single return
fix(zynqmp): modify function to have single return
fix(versal-net): add unsigned suffix to match data type
fix(versal): add unsigned suffix to match data type
fix(versal2): add missing curly braces
fix(versal-net): add missing curly braces
fix(zynqmp): add missing curly braces

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Merge "fix(xilinx): dcc console tests failing" into integration