rockchip/rk3399: Save space for DRAM suspend data

This removes the space allocation for the unused PHY register space.
For instance in PHY registers 0-127, only 0-90 are used, so don't save
the 91-1

rockchip/rk3399: Save space for DRAM suspend data

This removes the space allocation for the unused PHY register space.
For instance in PHY registers 0-127, only 0-90 are used, so don't save
the 91-127 registers. This saves about 1.6KB of space.

Change-Id: I0c9f6d9bed8f0c1f3b8b805dfb10cf0c06208919
Signed-off-by: Derek Basehore <dbasehore@chromium.org>

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rockchip: add pmusram section

the function pmu_cpuon_entrypoint() need to run in the pmusram,
we just copy bin file to pmusram before, now we add pmusram section
and link pmu_cpuon_entrypoint() to p

rockchip: add pmusram section

the function pmu_cpuon_entrypoint() need to run in the pmusram,
we just copy bin file to pmusram before, now we add pmusram section
and link pmu_cpuon_entrypoint() to pmusram directly

Change-Id: Iae31e4c01c480c8e6f565a8f588332b478efdb16
Signed-off-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

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rockchip/rk3399: fix DRAM gate training issue

The differential signal of DQS need keep low level
before gate training. It need enable RPULL and disable
PHY side ODT to ensure it when do gate trainin

rockchip/rk3399: fix DRAM gate training issue

The differential signal of DQS need keep low level
before gate training. It need enable RPULL and disable
PHY side ODT to ensure it when do gate training.
But it can not access the PHY registers to do it when
perform DFS.So the workaroud as below: It is ensure that
the PHY's read gate is landing somewhere in the incoming
DQS's pulses before it starts searching for pre-amble window.
It need get the rddqs_delay_ps to calculate the start point
of gate training for DFS.

Change-Id: I79eabcf4ec9a9c8f4539f68a51f22afba49c72fe
Signed-off-by: Lin Huang <hl@rock-chips.com>

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hikey960: support BL31

Support BL31 on HiKey960 platform. Implement PSCI.

Signed-off-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>

hikey960: support BL2

BL2 loads MCU firmware & BL31 on hikey960 platform. The MCU firmware
is used to implement low power feature.

Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>

hikey960: support BL1 on hikey960 platform

Support BL1 on HiKey960 platform. When recovery mode is detected,
BL1 loads NS BL1U that flushs images into UFS. When normal boot
mode is detected, BL1 loa

hikey960: support BL1 on hikey960 platform

Support BL1 on HiKey960 platform. When recovery mode is detected,
BL1 loads NS BL1U that flushs images into UFS. When normal boot
mode is detected, BL1 loads BL2.

Fix for https://github.com/ARM-software/tf-issues/issues/486

Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>

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hikey: enable PMF and instrumentations

enable PMF service call and instrumetion for hikey platform

Signed-off-by: Vincent Guittot <vincent.guittot@linaro.org>

Merge pull request #963 from soby-mathew/sm/scmi_dev

Add SCMI power domain and system power protocol support

Merge pull request #961 from jeenu-arm/gic-600

Introduce ARM GIC-600 driver

Merge pull request #960 from jeenu-arm/cpu-libs

Add support for Cortex-A75 and Cortex-A55 CPUs

Add SCMI support for Juno platform

This patch adds the memory map region for the SCMI payload memory
and maps the Juno core indices to SCMI power domains via the
`plat_css_core_pos_to_scmi_dmn_id_ma

Add SCMI support for Juno platform

This patch adds the memory map region for the SCMI payload memory
and maps the Juno core indices to SCMI power domains via the
`plat_css_core_pos_to_scmi_dmn_id_map` array.

Change-Id: I0d2bb2a719ff5b6a9d8e22e91e1625ab14453665
Signed-off-by: Soby Mathew <soby.mathew@arm.com>

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CSS: Add SCMI driver for SCP

This patch adds the SCMI driver for communicating with SCP. The power
domain management and system power management protocol of the SCMI
specification[1] is implemented

CSS: Add SCMI driver for SCP

This patch adds the SCMI driver for communicating with SCP. The power
domain management and system power management protocol of the SCMI
specification[1] is implemented in the driver. The SCP power management
abstraction layer for SCMI for CSS power management is also added.

A new buid option `CSS_USE_SCMI_DRIVER` is introduced to select SCMI
driver over SCPI.

[1] ARM System Control and Management Interface v1.0 (SCMI)
Document number: ARM DEN 0056A

Change-Id: I67265615a17e679a2afe810b9b0043711ba09dbb
Signed-off-by: Soby Mathew <soby.mathew@arm.com>

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Introduce ARM GIC-600 driver

ARM GIC-600 IP complies with ARM GICv3 architecture, but among others,
implements a power control register in the Redistributor frame. This
register must be programmed t

Introduce ARM GIC-600 driver

ARM GIC-600 IP complies with ARM GICv3 architecture, but among others,
implements a power control register in the Redistributor frame. This
register must be programmed to mark the frame as powered on, before
accessing other registers in the frame. Rest of initialization sequence
remains the same.

The driver provides APIs for Redistributor power management, and
overrides those in the generic GICv3 driver. The driver data is shared
between generic GICv3 driver and that of GIC-600.

For FVP platform, the GIC-600 driver is chosen when FVP_USE_GIC_DRIVER
is set to FVP_GIC600. Also update user guide.

Change-Id: I321b2360728d69f6d4b0a747b2cfcc3fe5a20d67
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>

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Add support for Cortex-A75 and Cortex-A55 CPUs

Both Cortex-A75 and Cortex-A55 CPUs use the ARM DynamIQ Shared Unit
(DSU). The power-down and power-up sequences are therefore mostly
managed in hardwa

Add support for Cortex-A75 and Cortex-A55 CPUs

Both Cortex-A75 and Cortex-A55 CPUs use the ARM DynamIQ Shared Unit
(DSU). The power-down and power-up sequences are therefore mostly
managed in hardware, and required software operations are considerably
simpler.

Change-Id: I68b30e6e1ebe7c041d5e67f39c59f08575fc7ecc
Co-authored-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>

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Merge pull request #957 from hzhuang1/finish_hikey_psci

Finish hikey psci

hikey: pm: finish PSCI hook functions

This patch is to enable CPU suspend/resume and system level's
suspend/resume; also enable system power off state.

Signed-off-by: Leo Yan <leo.yan@linaro.org>
S

hikey: pm: finish PSCI hook functions

This patch is to enable CPU suspend/resume and system level's
suspend/resume; also enable system power off state.

Signed-off-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>

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hikey: bl31: enable CCI port for cluster 0

The cluster 0 doesn't rely on PSCI to enable it; so enable CCI port
for cluster 0 in BL31 platform setup flow.

Signed-off-by: Leo Yan <leo.yan@linaro.org>

hikey: bl31: enable CCI port for cluster 0

The cluster 0 doesn't rely on PSCI to enable it; so enable CCI port
for cluster 0 in BL31 platform setup flow.

Signed-off-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>

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hikey: fix for CPU topology

Fix for CPU topology so present the CPU core numbers for two clusters;
Base on this fixing, the PSCI can maintain correct power states.

Signed-off-by: Leo Yan <leo.yan@l

hikey: fix for CPU topology

Fix for CPU topology so present the CPU core numbers for two clusters;
Base on this fixing, the PSCI can maintain correct power states.

Signed-off-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>

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hikey: fix uninitialized variable in ddr code

Fix uninitliazed variable in ddr driver code.

Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>

Merge pull request #949 from antonio-nino-diaz-arm/an/printf-memory

Reduce code size when building with Trusted Board Boot enabled

hikey: support BL31

Support BL31 and PSCI. Enable multiple cores in PSCI.

Change-Id: I66c39e1e9c4c45ac41a0142ed2070d79a3ac5ba3
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Signed-off-b

hikey: support BL31

Support BL31 and PSCI. Enable multiple cores in PSCI.

Change-Id: I66c39e1e9c4c45ac41a0142ed2070d79a3ac5ba3
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Signed-off-by: Dan Handley <dan.handley@arm.com>

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hikey: support BL2

BL2 is used to load BL31 and SCP_BL2. In HiKey platform, SCP_BL2
is the mcu firmware that is used to scale cpu frequency and switch
low power mode.

Change-Id: I1621aa65bea989fd12

hikey: support BL2

BL2 is used to load BL31 and SCP_BL2. In HiKey platform, SCP_BL2
is the mcu firmware that is used to scale cpu frequency and switch
low power mode.

Change-Id: I1621aa65bea989fd125ee8502fd56ef72362bf97
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Signed-off-by: Dan Handley <dan.handley@arm.com>

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hikey: support BL1

Initialize regulators, pins and eMMC in BL1. Only SRAM could be used in BL1.
So BL2 will be loaded from eMMC into SRAM later.

Change-Id: I8e7ef82ffa29a3c647c9d2d2981e8759ee85d833

hikey: support BL1

Initialize regulators, pins and eMMC in BL1. Only SRAM could be used in BL1.
So BL2 will be loaded from eMMC into SRAM later.

Change-Id: I8e7ef82ffa29a3c647c9d2d2981e8759ee85d833
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Signed-off-by: Dan Handley <dan.handley@arm.com>

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plat/arm: Compile out impossible conditional for AArch32

Since ARM_DRAM2_BASE is above the 32-bit limit, the condition
is always false. Wrap this condition in an ifndef to avoid
warnings during com

plat/arm: Compile out impossible conditional for AArch32

Since ARM_DRAM2_BASE is above the 32-bit limit, the condition
is always false. Wrap this condition in an ifndef to avoid
warnings during compilation.

Change-Id: Ideabb6c65de6c62474ed03eb29df4b049d5316be
Signed-off-by: dp-arm <dimitris.papastamos@arm.com>

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Remove plat_match_rotpk reference

This function was removed long ago. Remove remaining
pragma reference.

Change-Id: I66c556863d47dc17d2ffdc6c23aa524df6aade80
Signed-off-by: dp-arm <dimitris.papast

Remove plat_match_rotpk reference

This function was removed long ago. Remove remaining
pragma reference.

Change-Id: I66c556863d47dc17d2ffdc6c23aa524df6aade80
Signed-off-by: dp-arm <dimitris.papastamos@arm.com>

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