Merge pull request #890 from masahir0y/scp

Build: add generic way to include SCP_BL2 into FIP image

Merge pull request #897 from vwadekar/memctrl-v1-xlat-table-v2

Tegra: memctrl_v1: enable 'xlat_table_v2' library

Tegra: fix trivial misra issues

Not having U or ULL as a suffix for these enums causes
a lot of unnecessary MISRA issues. This patch adds U or
ULL suffix to these common enums to reduce number of
MI

Tegra: fix trivial misra issues

Not having U or ULL as a suffix for these enums causes
a lot of unnecessary MISRA issues. This patch adds U or
ULL suffix to these common enums to reduce number of
MISRA issues.

Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: no need to re-init the same console

This patch stops initialising the same UART console, as a "crash"
console. The normal and the crash consoles use the same UART port
and hence the crash con

Tegra: no need to re-init the same console

This patch stops initialising the same UART console, as a "crash"
console. The normal and the crash consoles use the same UART port
and hence the crash console init function now only checks if the
console is ready to be used.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: Add support for fake system suspend

This patch adds support for fake system suspend (SC7).
This is a debug mode, to ensure that a different code path is
executed for cases like pre-silicon de

Tegra: Add support for fake system suspend

This patch adds support for fake system suspend (SC7).
This is a debug mode, to ensure that a different code path is
executed for cases like pre-silicon development, where a
full-fledged SC7 is not possible in early stages.

This particular patch ensures that, if fake system suspend is
enabled (denoted by tegra_fake_system_suspend variable
having a non-zero value), instead of calling WFI, a request
for a warm reset is made for starting the SC7 exit procedure.

This ensures that the code path of kernel->ATF and back to
kernel is executed without depending on other components
involved in SC7 code path.

Additionally, this patch also adds support for SMC call
from kernel, enabling fake system suspend mode.

Signed-off-by: Vignesh Radhakrishnan <vigneshr@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: memctrl_v2: restore MC_TXN_OVERRIDE settings

This patch restores the MC_TXN_OVERRIDE settings when we exit from
System Suspend.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra: memctrl_v1: disable AHB redirection after cold boot

During boot, USB3 and flash media (SDMMC/SATA) devices need access to
IRAM. Because these clients connect to the MC and do not have a direc

Tegra: memctrl_v1: disable AHB redirection after cold boot

During boot, USB3 and flash media (SDMMC/SATA) devices need access to
IRAM. Because these clients connect to the MC and do not have a direct
path to the IRAM, the MC implements AHB redirection during boot to allow
path to IRAM. In this mode, accesses to a programmed memory address aperture
are directed to the AHB bus, allowing access to the IRAM. The AHB aperture
is defined by the IRAM_BASE_LO and IRAM_BASE_HI registers, which are
initialized to disable this aperture. Once bootup is complete, we must
program IRAM base/top, thus disabling access to IRAM.

This patch provides functionality to disable this access. The tegra port
calls this new function before jumping to the non-secure world during
cold boot.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: platform: support Tegra186 chip id

This patch adds support to read the chip id and identify if
the current platform is Tegra186.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra: memctrl_v2: MC transaction overrides for newer chips

This patch programs MC transaction overrides settings using
mc_txn_override_cfgs array for all Tegra chips beyond Tegra186
rev. A01

Signe

Tegra: memctrl_v2: MC transaction overrides for newer chips

This patch programs MC transaction overrides settings using
mc_txn_override_cfgs array for all Tegra chips beyond Tegra186
rev. A01

Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra186: mce: Avoid implementation-defined bitfield types

GCC version 4.8 (and presumably earlier) warn when non-standard types are
used for bitfield definitions when -pedantic is enabled. This pre

Tegra186: mce: Avoid implementation-defined bitfield types

GCC version 4.8 (and presumably earlier) warn when non-standard types are
used for bitfield definitions when -pedantic is enabled. This prevents TF
from being built with such toolchains, since -Werror -pedantic options are
used.

gcc-4.9 removed this warning; -pedantic is intended to cause gcc to emit a
warning in all cases required by the standard, but the standard does not
require a warning in this case.

See: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=57773

Signed-off-by: Stephen Warren <swarren@nvidia.com>

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Tegra: smmu: support for multiple devices

This patch adds flexibility to the code to initialise multiple SMMU
devices. The base address macro name has been changed to make it
explicit that we suppor

Tegra: smmu: support for multiple devices

This patch adds flexibility to the code to initialise multiple SMMU
devices. The base address macro name has been changed to make it
explicit that we support multiple SMMUs.

Change-Id: Id4854fb010ebeb699512d79c769de24050c2ad69
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: smmu: platform handler for SMMU settings

This patch empowers the platforms to provide an array with the
registers that must be saved/restored across System Suspend.

Original-change-by: Prite

Tegra: smmu: platform handler for SMMU settings

This patch empowers the platforms to provide an array with the
registers that must be saved/restored across System Suspend.

Original-change-by: Pritesh Raithatha <praithatha@nvidia.com>

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Merge pull request #895 from vwadekar/tegra186-platform-support-v5

Tegra186 platform support v5

Merge pull request #894 from Xilinx/errata-855873

zynqmp: Enable workaround for errata 855873

Merge pull request #885 from antonio-nino-diaz-arm/an/console-flush

Implement console_flush()

Tegra: memctrl_v1: enable 'xlat_table_v2' library

This patch enables the 'xlat_table_v2' library for the Tegra Memory
Controller driver. This library allows us to dynamically map/unmap
memory region

Tegra: memctrl_v1: enable 'xlat_table_v2' library

This patch enables the 'xlat_table_v2' library for the Tegra Memory
Controller driver. This library allows us to dynamically map/unmap
memory regions, with MMU enabled.

The Memory Controller driver maps/unmaps non-overlapping Video Memory
region, to clean it of any secure contents, before it resizes the
region.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: allow platforms to override plat_core_pos_by_mpidr()

This patch makes the default implementation of plat_core_pos_by_mpidr()
as weakly linked, so that platforms can override it with their own

Tegra: allow platforms to override plat_core_pos_by_mpidr()

This patch makes the default implementation of plat_core_pos_by_mpidr()
as weakly linked, so that platforms can override it with their own.

Tegra186, for one, does not have CPU IDs 2 and 3, so it has its own
implementation of plat_core_pos_by_mpidr().

Change-Id: I7a5319869c01ede3775386cb95af1431792f74b3
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: memctrl_v2: platform handler for MC settings

This patch empowers the platforms to provide the settings (e.g. stream ID,
security setting, transaction overrides) required by the Memory Control

Tegra: memctrl_v2: platform handler for MC settings

This patch empowers the platforms to provide the settings (e.g. stream ID,
security setting, transaction overrides) required by the Memory Controller
driver. This allows the platforms to program the Memory Controller as per
their needs and makes the driver scalable.

Original-change-by: Pritesh Raithatha <praithatha@nvidia.com>

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: memctrl_v2: remove non-secure access to TZSRAM memory

This patch removes the memory controller configuration setting, which
allowed non-secure access to the TZSRAM memory.

Change-Id: Ic13645

Tegra: memctrl_v2: remove non-secure access to TZSRAM memory

This patch removes the memory controller configuration setting, which
allowed non-secure access to the TZSRAM memory.

Change-Id: Ic13645ba6a7694f192565962df40ca4fb8130f23
Signed-off-by: Harvey Hsieh <hhsieh@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra186: mce: support for TEGRA_ARI_MISC_CCPLEX_EDBGREQ

This ARI call enables the EDBGREQ feature in the CCPLEX,
which will cause the CPUs to enter debug state instead of
vectoring to sw (ie MCA ha

Tegra186: mce: support for TEGRA_ARI_MISC_CCPLEX_EDBGREQ

This ARI call enables the EDBGREQ feature in the CCPLEX,
which will cause the CPUs to enter debug state instead of
vectoring to sw (ie MCA handler) upon receiving an async
abort signal.

Change-Id: Ifcb0e11446b6ac55179e3350d8f02b60ba32c94d
Signed-off-by: Rich Wiley <rwiley@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra186: update t18x_ari.h to v3.1

This patch updates the ARI header file to v3.1.

Change-Id: I3e58cf50d27fb6e72062bb9d9782b75296b32025
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra186: PSCI: support for 64-bit TZDRAM base

This patch fixes the variable width to store the TZDRAM base
address used to resume from System Suspend.

Change-Id: Ib67eda64b09f26fb2f427f0d624f05708

Tegra186: PSCI: support for 64-bit TZDRAM base

This patch fixes the variable width to store the TZDRAM base
address used to resume from System Suspend.

Change-Id: Ib67eda64b09f26fb2f427f0d624f057081473132
Signed-off-by: Steven Kao <skao@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: memctrl_v2: config to enable SMMU device

This patch adds a config to the memory controller driver to enable SMMU
device init during boot. Tegra186 platforms keeps it enabled by default,
but f

Tegra: memctrl_v2: config to enable SMMU device

This patch adds a config to the memory controller driver to enable SMMU
device init during boot. Tegra186 platforms keeps it enabled by default,
but future platforms might not support it.

Change-Id: Iebe1c60a25fc1cfb4c97a507e121d6685a49cb83
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra186: read activity monitor's clock counter values

This patch adds a new SMC function ID to read the refclk and coreclk
clock counter values from the Activity Monitor. The non-secure world
requi

Tegra186: read activity monitor's clock counter values

This patch adds a new SMC function ID to read the refclk and coreclk
clock counter values from the Activity Monitor. The non-secure world
requires this information to calculate the CPU's frequency.

Formula: "freq = (delta_coreclk / delta_refclk) * refclk_freq"

The following CPU registers have to be set by the non-secure driver
before issuing the SMC:

X1 = MPIDR of the target core
X2 = MIDR of the target core

Change-Id: I296d835def1f5788c17640c0c456b8f8f0e90824
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: memctrl_v2: make AFI device settings configurable

This patch adds a new config to enable MC settings for the AFIW
and AFIR devices. Platforms must enable this config on their own.

Change-Id:

Tegra: memctrl_v2: make AFI device settings configurable

This patch adds a new config to enable MC settings for the AFIW
and AFIR devices. Platforms must enable this config on their own.

Change-Id: I53b450117e4764ea76d9347ee2928f9be178b107
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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