| f51df475 | 23-Jul-2019 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
console: add a flag to prepend '\r' in the multi-console framework
Currently, console drivers prepend '\r' to '\n' by themselves. This is common enough to be supported in the framework.
Add a new f
console: add a flag to prepend '\r' in the multi-console framework
Currently, console drivers prepend '\r' to '\n' by themselves. This is common enough to be supported in the framework.
Add a new flag, CONSOLE_FLAG_TRANSLATE_CRLF. A driver can set this flag to ask the framework to transform LF into CRLF instead of doing it by itself.
Change-Id: I4f5c5887591bc0a8749a105abe62b6562eaf503b Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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| 960a12b3 | 16-Aug-2019 |
Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> |
intel: agilex: Clear PLL lostlock bypass mode
To provide glitchless clock to downstream logic even if clock toggles
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-
intel: agilex: Clear PLL lostlock bypass mode
To provide glitchless clock to downstream logic even if clock toggles
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I728d64d0ba3b4492125bea5b0737fc83180356f1
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| 988cc820 | 16-Aug-2019 |
Paul Beesley <paul.beesley@arm.com> |
Merge "FVP: Add Delay Timer driver to BL1 and BL31" into integration |
| 1b597c22 | 16-Aug-2019 |
Alexei Fedorov <Alexei.Fedorov@arm.com> |
FVP: Add Delay Timer driver to BL1 and BL31
SMMUv3 driver functions which are called from BL1 and BL31 currently use counter-based poll method for testing status bits. Adding Delay Timer driver to B
FVP: Add Delay Timer driver to BL1 and BL31
SMMUv3 driver functions which are called from BL1 and BL31 currently use counter-based poll method for testing status bits. Adding Delay Timer driver to BL1 and BL31 is required for timeout-based implementation using timer delay functions for SMMU and other drivers. This patch adds new function `fvp_timer_init()` which initialises either System level generic or SP804 timer based on FVP_USE_SP804_TIMER build flag. In BL2U `bl2u_early_platform_setup()` function the call to `arm_bl2u_early_platform_setup()` (which calls `generic_delay_timer_init()` ignoring FVP_USE_SP804_TIMER flag), is replaced with `arm_console_boot_init()` and `fvp_timer_init()`.
Change-Id: Ifd8dcebf4019e877b9bc5641551deef77a44c0d1 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
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| df51d8fe | 06-Aug-2019 |
Marek Vasut <marek.vasut+renesas@gmail.com> |
rcar_gen3: plat: Rename RCAR_PRODUCT_* to PRR_PRODUCT_*
Rename RCAR_PRODUCT_* to PRR_PRODUCT_* and drop the duplicate RCAR_PRODUCT_* macro.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com
rcar_gen3: plat: Rename RCAR_PRODUCT_* to PRR_PRODUCT_*
Rename RCAR_PRODUCT_* to PRR_PRODUCT_* and drop the duplicate RCAR_PRODUCT_* macro.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Change-Id: I6b2789790b85edb79c026f0860d70f323d113d96
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| 7c103d60 | 06-Aug-2019 |
Marek Vasut <marek.vasut+renesas@gmail.com> |
rcar_gen3: plat: Factor out PRR_ macros into rcar_def.h
Pull out the PRR_* macros into rcar_def.h and remove multiple copies of it. Now that there are still RCAR_* macros in rcar_def.h too and they
rcar_gen3: plat: Factor out PRR_ macros into rcar_def.h
Pull out the PRR_* macros into rcar_def.h and remove multiple copies of it. Now that there are still RCAR_* macros in rcar_def.h too and they have the exact same meaning as the PRR_* macros, but that's for another patch.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Change-Id: Icb7f61b971b1a23102bd1b9f58cda580660a55fc
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| 300df53b | 16-Aug-2019 |
Paul Beesley <paul.beesley@arm.com> |
Merge changes from topic "lm/juno_dyn_cfg" into integration
* changes: Juno: Use shared mbedtls heap between bl1 and bl2 Juno: add basic support for dynamic config |
| 544c092b | 29-May-2019 |
Ambroise Vincent <ambroise.vincent@arm.com> |
tegra: add support for multi console interface
This patch updates all Tegra platforms to use the new multi console API.
Change-Id: I27c0c7830a86e26491dea9991a689f0b01e4dbf0 Signed-off-by: Ambroise
tegra: add support for multi console interface
This patch updates all Tegra platforms to use the new multi console API.
Change-Id: I27c0c7830a86e26491dea9991a689f0b01e4dbf0 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com> Signed-off-by: Julius Werner <jwerner@chromium.org>
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| d1b6013d | 15-Aug-2019 |
Paul Beesley <paul.beesley@arm.com> |
Merge "intel: agilex: Fix memory controller driver" into integration |
| 99becbe3 | 15-Aug-2019 |
Paul Beesley <paul.beesley@arm.com> |
Merge changes from topic "rockchip-uart-fixes" into integration
* changes: rockchip: rk3399: store actual debug uart information on suspend rockchip: move dt-coreboot uart distinction into param
Merge changes from topic "rockchip-uart-fixes" into integration
* changes: rockchip: rk3399: store actual debug uart information on suspend rockchip: move dt-coreboot uart distinction into param handling code rockchip: make uart baudrate configurable rockchip: px30: add uart5 as option for serial output
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| b266d821 | 08-Aug-2019 |
Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> |
intel: agilex: Fix memory controller driver
Increase calibration delay, fix ddrio control config & nonsecure region limit
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> C
intel: agilex: Fix memory controller driver
Increase calibration delay, fix ddrio control config & nonsecure region limit
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: Ibca3c247a3ad5104176ca9057d29755599f13c9b
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| 4e865bd2 | 14-Aug-2019 |
Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> |
intel: agilex: Fix reliance on hard coded clock information
Extract clock information for UART, MMC & Watchdog from the clock manager
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@
intel: agilex: Fix reliance on hard coded clock information
Extract clock information for UART, MMC & Watchdog from the clock manager
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I42d3d4ceeaf45788d457472f6ddcd3fe099f0133
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| 9580f9bd | 31-Jul-2019 |
Louis Mayencourt <louis.mayencourt@arm.com> |
Juno: Use shared mbedtls heap between bl1 and bl2
Change-Id: Ia1ecad58ebf9de3f3a44b17ad1de57424b431125 Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com> |
| 8075fc59 | 29-Jul-2019 |
Louis Mayencourt <louis.mayencourt@arm.com> |
Juno: add basic support for dynamic config
Add the disable_auth dynamic parameter, that allows to disable the authentication when TBBR is enabled. This parameter is for development only.
Change-Id:
Juno: add basic support for dynamic config
Add the disable_auth dynamic parameter, that allows to disable the authentication when TBBR is enabled. This parameter is for development only.
Change-Id: Ic24ad16738517f7e07c4f506dcf69a1ae8df7d2d Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
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| fea24b88 | 30-Jul-2019 |
Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> |
intel: stratix10: Fix reliance on hard coded clock information
Extract clock information for UART, MMC & Watchdog from the platform rather than hard code it
Signed-off-by: Hadi Asyrafi <muhammad.ha
intel: stratix10: Fix reliance on hard coded clock information
Extract clock information for UART, MMC & Watchdog from the platform rather than hard code it
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I2582bd34a6da97bd75d5ccba5f93840e65f26b03
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| 0eb7fa91 | 05-Aug-2019 |
Heiko Stuebner <heiko@sntech.de> |
rockchip: rk3399: store actual debug uart information on suspend
The rk3399 suspend code saves and restores the debug uart settings, but right now always does this for the default uart. Right now th
rockchip: rk3399: store actual debug uart information on suspend
The rk3399 suspend code saves and restores the debug uart settings, but right now always does this for the default uart. Right now this works only by chance for the majority of rk3399 boards, which do not deviate from that default.
But both Coreboot as well as U-Boot-based platforms can actually use different uarts for their output, which can be configured from either devicetree or Coreboot-variables.
To fix this, just use the stored uart-base information instead of the default constant.
Signed-off-by: Heiko Stuebner <heiko@sntech.de> Change-Id: I1ea059d59a1126f6f8702315df7e620e632b686e
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| dd4a0d16 | 05-Aug-2019 |
Heiko Stuebner <heiko@sntech.de> |
rockchip: move dt-coreboot uart distinction into param handling code
Rockchip platforms can be booted from either u-boot or coreboot.
So far the Coreboot-console was initizalized from a coreboot da
rockchip: move dt-coreboot uart distinction into param handling code
Rockchip platforms can be booted from either u-boot or coreboot.
So far the Coreboot-console was initizalized from a coreboot data struct in the early_param2 callbacks and dt-based consoles with data from the rockchip_get_uart_* functions.
But later code may also need this console information for example for special suspend handling. To make this easy follow a suggestion from Julius Werner and move the coreboot<->dt distinction into the rockchip_get_uart_* functions, thus making correct data about the used uart available to all Rockchip platform code at all times.
This includes a new rockchip_get_uart_clock as well, because while the dt-platforms right now always just default the rate defined in a constant Coreboot provides its own field for the clock rate and we don't want to loose that information for the console init. Similarly the rk_uart_* variables should move into the non-Coreboot code, to prevent them from being marked as unused, which also requires the rk_get_uart_* functions to move below the actual dt-parsing.
Signed-off-by: Heiko Stuebner <heiko@sntech.de> Change-Id: I278d595d2aa6c6864187fc8979a9fbff9814feac
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| 5119fa7b | 07-Aug-2019 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge changes from topic "intel-plat-refactor" into integration
* changes: intel: Platform common code refactor intel: Platform common code refactor |
| 3f7b1490 | 01-Aug-2019 |
Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> |
intel: Platform common code refactor
Pull out common code from aarch64 and include
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I4d0f5e1bb01bcdacbedf8e6c359d
intel: Platform common code refactor
Pull out common code from aarch64 and include
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I4d0f5e1bb01bcdacbedf8e6c359de594239b645f
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| 7aed52cd | 06-Aug-2019 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge changes from topic "qemu_sbsa" into integration
* changes: plat/qemu: add gicv3 support for qemu plat/qemu: move gicv2 codes to separate file |
| 0d7b0963 | 06-Aug-2019 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge "meson: gxl: Fix CPU hotplug" into integration |
| 30970e0f | 05-Aug-2019 |
Heiko Stuebner <heiko@sntech.de> |
rockchip: make uart baudrate configurable
A previous patch already allowed to configure the uart output from the devicetree, but on Rockchip platforms we also have the issue of different vendors usi
rockchip: make uart baudrate configurable
A previous patch already allowed to configure the uart output from the devicetree, but on Rockchip platforms we also have the issue of different vendors using different baudrates for their uarts.
For example, rk3399 has a default baudrate of 115200 which is true for ChromeOS-devices and boards from Theobroma-Systems, while all the boards using the vendor boot chain actually use a baudrate of 1500000.
Similarly the newly added px30 has a default of said 1500000 but some boards may want to use the more widely used 115200.
The devicetree stdout-path node already contains the desired baudrate, so add simple code to parse it from there and override the default, which stays unchanged.
Signed-off-by: Heiko Stuebner <heiko@sntech.de> Change-Id: I7412139c3df3073a1996eb508ec08642ec6af90d
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| 5f441a7b | 05-Aug-2019 |
Heiko Stuebner <heiko@sntech.de> |
rockchip: px30: add uart5 as option for serial output
The px30 mini-evb can use either uart2 (muxed with the sd-card pins) or uart5 via its pin header for serial output. Uart5 is especially useful w
rockchip: px30: add uart5 as option for serial output
The px30 mini-evb can use either uart2 (muxed with the sd-card pins) or uart5 via its pin header for serial output. Uart5 is especially useful when needing to boot from the sd-card, where uart2 obviously is not useable.
So add the uart5 constants and it as uart option for the serial-param handler.
Signed-off-by: Heiko Stuebner <heiko@sntech.de> Change-Id: Ib88df7a55d761ee104d312c9953a13de3beba1c4
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| 35c28cc9 | 02-Aug-2019 |
Alexei Fedorov <Alexei.Fedorov@arm.com> |
Merge "intel: stratix10: Fix BL31 memory mapping" into integration |
| a91e9043 | 02-Aug-2019 |
Alexei Fedorov <Alexei.Fedorov@arm.com> |
Merge "meson: gxl: Fix reset and power off" into integration |