1 /* 2 * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <platform_def.h> 10 11 #include <arch.h> 12 #include <arch_features.h> 13 #include <arch_helpers.h> 14 #include <bl1/bl1.h> 15 #include <common/bl_common.h> 16 #include <common/debug.h> 17 #include <drivers/auth/auth_mod.h> 18 #include <drivers/console.h> 19 #include <lib/cpus/errata_report.h> 20 #include <lib/utils.h> 21 #include <plat/common/platform.h> 22 #include <smccc_helpers.h> 23 #include <tools_share/uuid.h> 24 25 #include "bl1_private.h" 26 27 /* BL1 Service UUID */ 28 DEFINE_SVC_UUID2(bl1_svc_uid, 29 0xd46739fd, 0xcb72, 0x9a4d, 0xb5, 0x75, 30 0x67, 0x15, 0xd6, 0xf4, 0xbb, 0x4a); 31 32 static void bl1_load_bl2(void); 33 34 /******************************************************************************* 35 * Helper utility to calculate the BL2 memory layout taking into consideration 36 * the BL1 RW data assuming that it is at the top of the memory layout. 37 ******************************************************************************/ 38 void bl1_calc_bl2_mem_layout(const meminfo_t *bl1_mem_layout, 39 meminfo_t *bl2_mem_layout) 40 { 41 assert(bl1_mem_layout != NULL); 42 assert(bl2_mem_layout != NULL); 43 44 /* 45 * Remove BL1 RW data from the scope of memory visible to BL2. 46 * This is assuming BL1 RW data is at the top of bl1_mem_layout. 47 */ 48 assert(BL1_RW_BASE > bl1_mem_layout->total_base); 49 bl2_mem_layout->total_base = bl1_mem_layout->total_base; 50 bl2_mem_layout->total_size = BL1_RW_BASE - bl1_mem_layout->total_base; 51 52 flush_dcache_range((unsigned long)bl2_mem_layout, sizeof(meminfo_t)); 53 } 54 55 /******************************************************************************* 56 * Setup function for BL1. 57 ******************************************************************************/ 58 void bl1_setup(void) 59 { 60 /* Perform early platform-specific setup */ 61 bl1_early_platform_setup(); 62 63 /* Perform late platform-specific setup */ 64 bl1_plat_arch_setup(); 65 66 #if CTX_INCLUDE_PAUTH_REGS 67 /* 68 * Assert that the ARMv8.3-PAuth registers are present or an access 69 * fault will be triggered when they are being saved or restored. 70 */ 71 assert(is_armv8_3_pauth_present()); 72 #endif /* CTX_INCLUDE_PAUTH_REGS */ 73 } 74 75 /******************************************************************************* 76 * Function to perform late architectural and platform specific initialization. 77 * It also queries the platform to load and run next BL image. Only called 78 * by the primary cpu after a cold boot. 79 ******************************************************************************/ 80 void bl1_main(void) 81 { 82 unsigned int image_id; 83 84 /* Announce our arrival */ 85 NOTICE(FIRMWARE_WELCOME_STR); 86 NOTICE("BL1: %s\n", version_string); 87 NOTICE("BL1: %s\n", build_message); 88 89 INFO("BL1: RAM %p - %p\n", (void *)BL1_RAM_BASE, 90 (void *)BL1_RAM_LIMIT); 91 92 print_errata_status(); 93 94 #if ENABLE_ASSERTIONS 95 u_register_t val; 96 /* 97 * Ensure that MMU/Caches and coherency are turned on 98 */ 99 #ifdef __aarch64__ 100 val = read_sctlr_el3(); 101 #else 102 val = read_sctlr(); 103 #endif 104 assert(val & SCTLR_M_BIT); 105 assert(val & SCTLR_C_BIT); 106 assert(val & SCTLR_I_BIT); 107 /* 108 * Check that Cache Writeback Granule (CWG) in CTR_EL0 matches the 109 * provided platform value 110 */ 111 val = (read_ctr_el0() >> CTR_CWG_SHIFT) & CTR_CWG_MASK; 112 /* 113 * If CWG is zero, then no CWG information is available but we can 114 * at least check the platform value is less than the architectural 115 * maximum. 116 */ 117 if (val != 0) 118 assert(CACHE_WRITEBACK_GRANULE == SIZE_FROM_LOG2_WORDS(val)); 119 else 120 assert(CACHE_WRITEBACK_GRANULE <= MAX_CACHE_LINE_SIZE); 121 #endif /* ENABLE_ASSERTIONS */ 122 123 /* Perform remaining generic architectural setup from EL3 */ 124 bl1_arch_setup(); 125 126 #if TRUSTED_BOARD_BOOT 127 /* Initialize authentication module */ 128 auth_mod_init(); 129 #endif /* TRUSTED_BOARD_BOOT */ 130 131 /* Perform platform setup in BL1. */ 132 bl1_platform_setup(); 133 134 /* Get the image id of next image to load and run. */ 135 image_id = bl1_plat_get_next_image_id(); 136 137 /* 138 * We currently interpret any image id other than 139 * BL2_IMAGE_ID as the start of firmware update. 140 */ 141 if (image_id == BL2_IMAGE_ID) 142 bl1_load_bl2(); 143 else 144 NOTICE("BL1-FWU: *******FWU Process Started*******\n"); 145 146 bl1_prepare_next_image(image_id); 147 148 console_flush(); 149 } 150 151 /******************************************************************************* 152 * This function locates and loads the BL2 raw binary image in the trusted SRAM. 153 * Called by the primary cpu after a cold boot. 154 * TODO: Add support for alternative image load mechanism e.g using virtio/elf 155 * loader etc. 156 ******************************************************************************/ 157 static void bl1_load_bl2(void) 158 { 159 image_desc_t *image_desc; 160 image_info_t *image_info; 161 int err; 162 163 /* Get the image descriptor */ 164 image_desc = bl1_plat_get_image_desc(BL2_IMAGE_ID); 165 assert(image_desc); 166 167 /* Get the image info */ 168 image_info = &image_desc->image_info; 169 INFO("BL1: Loading BL2\n"); 170 171 err = bl1_plat_handle_pre_image_load(BL2_IMAGE_ID); 172 if (err) { 173 ERROR("Failure in pre image load handling of BL2 (%d)\n", err); 174 plat_error_handler(err); 175 } 176 177 err = load_auth_image(BL2_IMAGE_ID, image_info); 178 if (err) { 179 ERROR("Failed to load BL2 firmware.\n"); 180 plat_error_handler(err); 181 } 182 183 /* Allow platform to handle image information. */ 184 err = bl1_plat_handle_post_image_load(BL2_IMAGE_ID); 185 if (err) { 186 ERROR("Failure in post image load handling of BL2 (%d)\n", err); 187 plat_error_handler(err); 188 } 189 190 NOTICE("BL1: Booting BL2\n"); 191 } 192 193 /******************************************************************************* 194 * Function called just before handing over to the next BL to inform the user 195 * about the boot progress. In debug mode, also print details about the BL 196 * image's execution context. 197 ******************************************************************************/ 198 void bl1_print_next_bl_ep_info(const entry_point_info_t *bl_ep_info) 199 { 200 #ifdef __aarch64__ 201 NOTICE("BL1: Booting BL31\n"); 202 #else 203 NOTICE("BL1: Booting BL32\n"); 204 #endif /* __aarch64__ */ 205 print_entry_point_info(bl_ep_info); 206 } 207 208 #if SPIN_ON_BL1_EXIT 209 void print_debug_loop_message(void) 210 { 211 NOTICE("BL1: Debug loop, spinning forever\n"); 212 NOTICE("BL1: Please connect the debugger to continue\n"); 213 } 214 #endif 215 216 /******************************************************************************* 217 * Top level handler for servicing BL1 SMCs. 218 ******************************************************************************/ 219 register_t bl1_smc_handler(unsigned int smc_fid, 220 register_t x1, 221 register_t x2, 222 register_t x3, 223 register_t x4, 224 void *cookie, 225 void *handle, 226 unsigned int flags) 227 { 228 229 #if TRUSTED_BOARD_BOOT 230 /* 231 * Dispatch FWU calls to FWU SMC handler and return its return 232 * value 233 */ 234 if (is_fwu_fid(smc_fid)) { 235 return bl1_fwu_smc_handler(smc_fid, x1, x2, x3, x4, cookie, 236 handle, flags); 237 } 238 #endif 239 240 switch (smc_fid) { 241 case BL1_SMC_CALL_COUNT: 242 SMC_RET1(handle, BL1_NUM_SMC_CALLS); 243 244 case BL1_SMC_UID: 245 SMC_UUID_RET(handle, bl1_svc_uid); 246 247 case BL1_SMC_VERSION: 248 SMC_RET1(handle, BL1_SMC_MAJOR_VER | BL1_SMC_MINOR_VER); 249 250 default: 251 break; 252 } 253 254 WARN("Unimplemented BL1 SMC Call: 0x%x \n", smc_fid); 255 SMC_RET1(handle, SMC_UNK); 256 } 257 258 /******************************************************************************* 259 * BL1 SMC wrapper. This function is only used in AArch32 mode to ensure ABI 260 * compliance when invoking bl1_smc_handler. 261 ******************************************************************************/ 262 register_t bl1_smc_wrapper(uint32_t smc_fid, 263 void *cookie, 264 void *handle, 265 unsigned int flags) 266 { 267 register_t x1, x2, x3, x4; 268 269 assert(handle); 270 271 get_smc_params_from_ctx(handle, x1, x2, x3, x4); 272 return bl1_smc_handler(smc_fid, x1, x2, x3, x4, cookie, handle, flags); 273 } 274