1 /* 2 * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <platform_def.h> 10 11 #include <arch_helpers.h> 12 #include <common/bl_common.h> 13 #include <common/debug.h> 14 #include <bl31/interrupt_mgmt.h> 15 #include <drivers/console.h> 16 #include <drivers/ti/uart/uart_16550.h> 17 #include <lib/xlat_tables/xlat_tables_v2.h> 18 19 #include <rpi_hw.h> 20 #include <rpi_shared.h> 21 22 #define MAP_DEVICE0 MAP_REGION_FLAT(DEVICE0_BASE, \ 23 DEVICE0_SIZE, \ 24 MT_DEVICE | MT_RW | MT_SECURE) 25 26 #define MAP_SHARED_RAM MAP_REGION_FLAT(SHARED_RAM_BASE, \ 27 SHARED_RAM_SIZE, \ 28 MT_DEVICE | MT_RW | MT_SECURE) 29 30 #ifdef RPI3_PRELOADED_DTB_BASE 31 #define MAP_NS_DTB MAP_REGION_FLAT(RPI3_PRELOADED_DTB_BASE, 0x10000, \ 32 MT_MEMORY | MT_RW | MT_NS) 33 #endif 34 35 #define MAP_NS_DRAM0 MAP_REGION_FLAT(NS_DRAM0_BASE, NS_DRAM0_SIZE, \ 36 MT_MEMORY | MT_RW | MT_NS) 37 38 #define MAP_FIP MAP_REGION_FLAT(PLAT_RPI3_FIP_BASE, \ 39 PLAT_RPI3_FIP_MAX_SIZE, \ 40 MT_MEMORY | MT_RO | MT_NS) 41 42 #define MAP_BL32_MEM MAP_REGION_FLAT(BL32_MEM_BASE, BL32_MEM_SIZE, \ 43 MT_MEMORY | MT_RW | MT_SECURE) 44 45 #ifdef SPD_opteed 46 #define MAP_OPTEE_PAGEABLE MAP_REGION_FLAT( \ 47 RPI3_OPTEE_PAGEABLE_LOAD_BASE, \ 48 RPI3_OPTEE_PAGEABLE_LOAD_SIZE, \ 49 MT_MEMORY | MT_RW | MT_SECURE) 50 #endif 51 52 /* 53 * Table of regions for various BL stages to map using the MMU. 54 */ 55 #ifdef IMAGE_BL1 56 static const mmap_region_t plat_rpi3_mmap[] = { 57 MAP_SHARED_RAM, 58 MAP_DEVICE0, 59 MAP_FIP, 60 #ifdef SPD_opteed 61 MAP_OPTEE_PAGEABLE, 62 #endif 63 {0} 64 }; 65 #endif 66 67 #ifdef IMAGE_BL2 68 static const mmap_region_t plat_rpi3_mmap[] = { 69 MAP_SHARED_RAM, 70 MAP_DEVICE0, 71 MAP_FIP, 72 MAP_NS_DRAM0, 73 #ifdef BL32_BASE 74 MAP_BL32_MEM, 75 #endif 76 {0} 77 }; 78 #endif 79 80 #ifdef IMAGE_BL31 81 static const mmap_region_t plat_rpi3_mmap[] = { 82 MAP_SHARED_RAM, 83 MAP_DEVICE0, 84 #ifdef RPI3_PRELOADED_DTB_BASE 85 MAP_NS_DTB, 86 #endif 87 #ifdef BL32_BASE 88 MAP_BL32_MEM, 89 #endif 90 {0} 91 }; 92 #endif 93 94 /******************************************************************************* 95 * Function that sets up the console 96 ******************************************************************************/ 97 static console_16550_t rpi3_console; 98 99 void rpi3_console_init(void) 100 { 101 int console_scope = CONSOLE_FLAG_BOOT; 102 #if RPI3_RUNTIME_UART != -1 103 console_scope |= CONSOLE_FLAG_RUNTIME; 104 #endif 105 int rc = console_16550_register(PLAT_RPI3_UART_BASE, 106 PLAT_RPI3_UART_CLK_IN_HZ, 107 PLAT_RPI3_UART_BAUDRATE, 108 &rpi3_console); 109 if (rc == 0) { 110 /* 111 * The crash console doesn't use the multi console API, it uses 112 * the core console functions directly. It is safe to call panic 113 * and let it print debug information. 114 */ 115 panic(); 116 } 117 118 console_set_scope(&rpi3_console.console, console_scope); 119 } 120 121 /******************************************************************************* 122 * Function that sets up the translation tables. 123 ******************************************************************************/ 124 void rpi3_setup_page_tables(uintptr_t total_base, size_t total_size, 125 uintptr_t code_start, uintptr_t code_limit, 126 uintptr_t rodata_start, uintptr_t rodata_limit 127 #if USE_COHERENT_MEM 128 , uintptr_t coh_start, uintptr_t coh_limit 129 #endif 130 ) 131 { 132 /* 133 * Map the Trusted SRAM with appropriate memory attributes. 134 * Subsequent mappings will adjust the attributes for specific regions. 135 */ 136 VERBOSE("Trusted SRAM seen by this BL image: %p - %p\n", 137 (void *) total_base, (void *) (total_base + total_size)); 138 mmap_add_region(total_base, total_base, 139 total_size, 140 MT_MEMORY | MT_RW | MT_SECURE); 141 142 /* Re-map the code section */ 143 VERBOSE("Code region: %p - %p\n", 144 (void *) code_start, (void *) code_limit); 145 mmap_add_region(code_start, code_start, 146 code_limit - code_start, 147 MT_CODE | MT_SECURE); 148 149 /* Re-map the read-only data section */ 150 VERBOSE("Read-only data region: %p - %p\n", 151 (void *) rodata_start, (void *) rodata_limit); 152 mmap_add_region(rodata_start, rodata_start, 153 rodata_limit - rodata_start, 154 MT_RO_DATA | MT_SECURE); 155 156 #if USE_COHERENT_MEM 157 /* Re-map the coherent memory region */ 158 VERBOSE("Coherent region: %p - %p\n", 159 (void *) coh_start, (void *) coh_limit); 160 mmap_add_region(coh_start, coh_start, 161 coh_limit - coh_start, 162 MT_DEVICE | MT_RW | MT_SECURE); 163 #endif 164 165 mmap_add(plat_rpi3_mmap); 166 167 init_xlat_tables(); 168 } 169 170 /******************************************************************************* 171 * Return entrypoint of BL33. 172 ******************************************************************************/ 173 uintptr_t plat_get_ns_image_entrypoint(void) 174 { 175 #ifdef PRELOADED_BL33_BASE 176 return PRELOADED_BL33_BASE; 177 #else 178 return PLAT_RPI3_NS_IMAGE_OFFSET; 179 #endif 180 } 181 182 /******************************************************************************* 183 * Gets SPSR for BL32 entry 184 ******************************************************************************/ 185 uint32_t rpi3_get_spsr_for_bl32_entry(void) 186 { 187 /* 188 * The Secure Payload Dispatcher service is responsible for 189 * setting the SPSR prior to entry into the BL32 image. 190 */ 191 return 0; 192 } 193 194 /******************************************************************************* 195 * Gets SPSR for BL33 entry 196 ******************************************************************************/ 197 uint32_t rpi3_get_spsr_for_bl33_entry(void) 198 { 199 #if RPI3_BL33_IN_AARCH32 200 INFO("BL33 will boot in Non-secure AArch32 Hypervisor mode\n"); 201 return SPSR_MODE32(MODE32_hyp, SPSR_T_ARM, SPSR_E_LITTLE, 202 DISABLE_ALL_EXCEPTIONS); 203 #else 204 return SPSR_64(MODE_EL2, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 205 #endif 206 } 207 208 unsigned int plat_get_syscnt_freq2(void) 209 { 210 return SYS_COUNTER_FREQ_IN_TICKS; 211 } 212 213 uint32_t plat_ic_get_pending_interrupt_type(void) 214 { 215 ERROR("rpi3: Interrupt routed to EL3.\n"); 216 return INTR_TYPE_INVAL; 217 } 218 219 uint32_t plat_interrupt_type_to_line(uint32_t type, uint32_t security_state) 220 { 221 assert((type == INTR_TYPE_S_EL1) || (type == INTR_TYPE_EL3) || 222 (type == INTR_TYPE_NS)); 223 224 assert(sec_state_is_valid(security_state)); 225 226 /* Non-secure interrupts are signalled on the IRQ line always. */ 227 if (type == INTR_TYPE_NS) 228 return __builtin_ctz(SCR_IRQ_BIT); 229 230 /* Secure interrupts are signalled on the FIQ line always. */ 231 return __builtin_ctz(SCR_FIQ_BIT); 232 } 233