| d82f5a36 | 07-Mar-2017 |
Steven Kao <skao@nvidia.com> |
Tegra194: add 'TEGRA_TMRUS_SIZE' macro
This patch defines the macro for the TEGRA_TMRUS aperture size.
Change-Id: I33fb674c6a7be8d02971667e7bf8650b7adc62ef
Signed-off-by: Steven Kao <skao@nvidia.co
Tegra194: add 'TEGRA_TMRUS_SIZE' macro
This patch defines the macro for the TEGRA_TMRUS aperture size.
Change-Id: I33fb674c6a7be8d02971667e7bf8650b7adc62ef
Signed-off-by: Steven Kao <skao@nvidia.com>
show more ...
|
| ddbf946f | 20-Mar-2017 |
Stefan Kristiansson <stefank@nvidia.com> |
Tegra194: Fix TEGRA186_SMMU_CTX_SIZE
TEGRA186_SMMU_CTX_SIZE should match the numbe of elements
in smmu_ctx_regs, which is defined in smmu_plat_config.h.
The current number of elements are 0x490.
Ch
Tegra194: Fix TEGRA186_SMMU_CTX_SIZE
TEGRA186_SMMU_CTX_SIZE should match the numbe of elements
in smmu_ctx_regs, which is defined in smmu_plat_config.h.
The current number of elements are 0x490.
Change-Id: If0614ea8ef8b6a8f5da1a3279abaf9255eb76420
Signed-off-by: Stefan Kristiansson <stefank@nvidia.com>
show more ...
|
| 4fb71eae | 03-Mar-2017 |
Rohit Khanna <rokhanna@nvidia.com> |
Tegra194: Dont run MCE firmware on Emulation
Dont run MCE firmware on pre-silicon emulation platforms
Change-Id: I2a8d653e46f494621580ca92271a18e62f648859
Signed-off-by: Rohit Khanna <rokhanna@nvid
Tegra194: Dont run MCE firmware on Emulation
Dont run MCE firmware on pre-silicon emulation platforms
Change-Id: I2a8d653e46f494621580ca92271a18e62f648859
Signed-off-by: Rohit Khanna <rokhanna@nvidia.com>
show more ...
|
| e9bb627d | 13-Feb-2017 |
Pritesh Raithatha <praithatha@nvidia.com> |
Tegra194: remove GPU, MPCORE and PTC registers from streamid list
GPU, MPCORE and PTC clients are changed and not going through SMMU.
Removing it from streamid list.
Change-Id: I14b450a11f02ad6c1a9
Tegra194: remove GPU, MPCORE and PTC registers from streamid list
GPU, MPCORE and PTC clients are changed and not going through SMMU.
Removing it from streamid list.
Change-Id: I14b450a11f02ad6c1a97e67e487d6d624911d019
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
show more ...
|
| 7e4ffcd9 | 22-Feb-2017 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra194: Support SMC64 encoding for MCE calls
This patch uses SMC64 encoding for all MCE SMC calls originating
from the linux kernel.
Change-Id: Ic4633de5c638566012db033bbaf8c9d9343acdc0
Signed-of
Tegra194: Support SMC64 encoding for MCE calls
This patch uses SMC64 encoding for all MCE SMC calls originating
from the linux kernel.
Change-Id: Ic4633de5c638566012db033bbaf8c9d9343acdc0
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
show more ...
|
| 9808032c | 05-Jan-2017 |
Steven Kao <skao@nvidia.com> |
Tegra194: Enable MCE driver
This patch enable MCE driver for T19x SoC. The MCE driver
takes care of the communication with the MCE firmware to
achieve:
- Cold boot
- Warm boot
- Core/Cluster/System
Tegra194: Enable MCE driver
This patch enable MCE driver for T19x SoC. The MCE driver
takes care of the communication with the MCE firmware to
achieve:
- Cold boot
- Warm boot
- Core/Cluster/System Power management
- Custom MCE requests
Change-Id: I75854c0b649a691e9b244d9ed9fc1c19743e3e8d
Signed-off-by: Steven Kao <skao@nvidia.com>
show more ...
|
| 5660eebf | 24-Jan-2017 |
Pritesh Raithatha <praithatha@nvidia.com> |
Tegra194: enable SMMU
Enable smmu by setting ENABLE_SMMU_DEVICE to 1.
Change-Id: I9135071b257a166fa6082b7fe409bcd315cf6838
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com> |
| 0ea8881e | 24-Jan-2017 |
Pritesh Raithatha <praithatha@nvidia.com> |
Tegra194: add support for multiple SMMU devices
This patch adds support for all three SMMU devices present on the SoC.
The following changes have been done:
Add SMMU devices to the memory map
Tegra194: add support for multiple SMMU devices
This patch adds support for all three SMMU devices present on the SoC.
The following changes have been done:
Add SMMU devices to the memory map
Update register read and write functions
Change-Id: I0007b496d2ae7264f4fa9f605d4b0a15fa747a0f
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
show more ...
|
| 2ac8cb7e | 02-Jan-2017 |
Pritesh Raithatha <praithatha@nvidia.com> |
Tegra194: add SMMU and mc_sid support
Define mc sid and txn override regs and sec cfgs.
Create array for mc sid override regs and sec config that is
used to initialize mc.
Add smmu ctx regs array to
Tegra194: add SMMU and mc_sid support
Define mc sid and txn override regs and sec cfgs.
Create array for mc sid override regs and sec config that is
used to initialize mc.
Add smmu ctx regs array to hold register values during suspend.
Change-Id: I7b265710a9ec2be7dea050058bce65c614772c78
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
show more ...
|
| d11c793b | 23-Dec-2016 |
Steven Kao <skao@nvidia.com> |
Tegra194: psci: support for 64-bit TZDRAM base
This patch fixes the variable width to store the TZDRAM base
address used to resume from System Suspend.
Change-Id: I3c18eb844963f39f91b5ac45e3709f335
Tegra194: psci: support for 64-bit TZDRAM base
This patch fixes the variable width to store the TZDRAM base
address used to resume from System Suspend.
Change-Id: I3c18eb844963f39f91b5ac45e3709f3354bcda0c
Signed-off-by: Steven Kao <skao@nvidia.com>
show more ...
|
| 41612559 | 10-Apr-2018 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra194: base commit for the platform
This patch creates the base commit for the Tegra194 platform, from
Tegra186 code base.
Change-Id: I1c77e4984f7ff39655f3fb79633d13d533707ede
Signed-off-by: Var
Tegra194: base commit for the platform
This patch creates the base commit for the Tegra194 platform, from
Tegra186 code base.
Change-Id: I1c77e4984f7ff39655f3fb79633d13d533707ede
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
show more ...
|
| cf489bf1 | 25-May-2017 |
Vignesh Radhakrishnan <vigneshr@nvidia.com> |
Revert "Tegra: Add support for fake system suspend"
This reverts commit c41df8fda84b9bc56bbb2347fb902f64b1bb557e
Fake system suspend relies on software running on EL3
to trigger a warm reset.
Reve
Revert "Tegra: Add support for fake system suspend"
This reverts commit c41df8fda84b9bc56bbb2347fb902f64b1bb557e
Fake system suspend relies on software running on EL3
to trigger a warm reset.
Revert enabling fake system suspend, as the software
running on El3 is not allowed to trigger a warm reset.
Change-Id: I6035f2a7bcb0a4ad50a62c5bc5239226c625ee5e
Signed-off-by: Vignesh Radhakrishnan <vigneshr@nvidia.com>
show more ...
|
| b30646a8 | 18-Oct-2019 |
Manish Pandey <manish.pandey2@arm.com> |
plat/arm: use Aff3 bits also to validate mpidr
There are some platforms which uses MPIDR Affinity level 3 for storing
extra affinity information e.g. N1SDP uses it for keeping chip id in a
multichip
plat/arm: use Aff3 bits also to validate mpidr
There are some platforms which uses MPIDR Affinity level 3 for storing
extra affinity information e.g. N1SDP uses it for keeping chip id in a
multichip setup, for such platforms MPIDR validation should not fail.
This patch adds Aff3 bits also as part of mpidr validation mask, for
platforms which does not uses Aff3 will not have any impact as these
bits will be all zeros.
Change-Id: Ia8273972fa7948fdb11708308d0239d2dc4dfa85
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
show more ...
|
| 0711ee5c | 24-Sep-2019 |
Lionel Debieve <lionel.debieve@st.com> |
delay: timeout detection support
Introduce timeout_init_us/timeout_elapsed() delay tracking with CNTPCT.
timeout_init_us(some_timeout_us); returns a reference to detect
timeout for the provided mic
delay: timeout detection support
Introduce timeout_init_us/timeout_elapsed() delay tracking with CNTPCT.
timeout_init_us(some_timeout_us); returns a reference to detect
timeout for the provided microsecond delay value from current time.
timeout_elapsed(reference) return true/false whether the reference
timeout is elapsed.
Cherry picked from OP-TEE implementation [1].
[1] commit 33d30a74502b ("core: timeout detection support")
Minor:
- Remove stm32mp platform duplicated implementation.
- Add new include in marvell ble.mk
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Change-Id: Iaef6d43c11a2e6992fb48efdc674a0552755ad9c
show more ...
|
| 78f02ae2 | 22-Jul-2019 |
Imre Kis <imre.kis@arm.com> |
Introducing support for Cortex-A65AE
Change-Id: I1ea2bf088f1e001cdbd377cbfb7c6a2866af0422
Signed-off-by: Imre Kis <imre.kis@arm.com> |
| efcf951f | 03-Oct-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge changes from topic "qemu_sbsa" into integration
* changes:
qemu/qemu_sbsa: Adding memory mapping for both FLASH0/FLASH1
qemu/qemu_sbsa: Adding Qemu SBSA platform |
| 82d8d4ab | 03-Oct-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge changes I0355e084,I6a6dd1c0 into integration
* changes:
mediatek: mt8183: add EMI MPU driver for DRAM protection
mediatek: mt8183: add DEVAPC driver to control protection |
| 251b2643 | 03-Oct-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge "a5ds: Add handler for when user tries to switch off secondary cores" into integration |
| 59ffec15 | 26-Sep-2019 |
Usama Arif <usama.arif@arm.com> |
a5ds: Add handler for when user tries to switch off secondary cores
a5ds only has always-on power domain and there is no power control
present. However, without the pwr_domain_off handler, the kerne
a5ds: Add handler for when user tries to switch off secondary cores
a5ds only has always-on power domain and there is no power control
present. However, without the pwr_domain_off handler, the kernel
panics when the user will try to switch off secondary cores. The
a5ds_pwr_domain_off handler will prevent kernel from crashing,
i.e. the kernel will attempt but fail to shut down the secondary CPUs
if the user tries to switch them offline.
Change-Id: I3c2239a1b6f035113ddbdda063c8495000cbe30c
Signed-off-by: Usama Arif <usama.arif@arm.com>
show more ...
|
| f25ea7e3 | 23-Aug-2019 |
kenny liang <kenny.liang@mediatek.com> |
mediatek: mt8183: add EMI MPU driver for DRAM protection
Add EMI MPU driver for DRAM protection.
Signed-off-by: kenny liang <kenny.liang@mediatek.com>
Change-Id: I0355e084184b5396ad8ac99fff6ef9d050
mediatek: mt8183: add EMI MPU driver for DRAM protection
Add EMI MPU driver for DRAM protection.
Signed-off-by: kenny liang <kenny.liang@mediatek.com>
Change-Id: I0355e084184b5396ad8ac99fff6ef9d050fb5e96
show more ...
|
| 1b0174ef | 23-Aug-2019 |
kenny liang <kenny.liang@mediatek.com> |
mediatek: mt8183: add DEVAPC driver to control protection
Add DEVAPC driver to control protection.
Signed-off-by: kenny liang <kenny.liang@mediatek.com>
Change-Id: I6a6dd1c0bffa372b6df2cb604ca5e02e
mediatek: mt8183: add DEVAPC driver to control protection
Add DEVAPC driver to control protection.
Signed-off-by: kenny liang <kenny.liang@mediatek.com>
Change-Id: I6a6dd1c0bffa372b6df2cb604ca5e02eabbb9d26
show more ...
|
| 6ad216dc | 18-Jul-2019 |
Imre Kis <imre.kis@arm.com> |
Introducing support for Cortex-A65
Change-Id: I645442d52a295706948e2cac88c36c1a3cb0bc47
Signed-off-by: Imre Kis <imre.kis@arm.com> |
| fa405e3b | 07-Jun-2018 |
Radoslaw Biernacki <radoslaw.biernacki@linaro.org> |
qemu/qemu_sbsa: Adding memory mapping for both FLASH0/FLASH1
This patch adds mapping for secure FLASH0 for qemu/virt and
qemu/qemu_sbsa platforms. This change is targeted for sbsa but since both
pla
qemu/qemu_sbsa: Adding memory mapping for both FLASH0/FLASH1
This patch adds mapping for secure FLASH0 for qemu/virt and
qemu/qemu_sbsa platforms. This change is targeted for sbsa but since both
platforms share common code, changes in common defines was necessary.
For qemu_sbsa, this patch adds necessary mapping in order to boot without
semi-hosting from secure FLASH0. EFI need to stay in FLASH1 (share it with
variables) since it need to "run in place" in non secure domain. Changes
for this are under RFC at edk2-platforms mailing list:
https://patches.linaro.org/patch/171327/
(edk2-platforms/Platform/Qemu/SbsaQemu/SbsaQemu.dsc).
In docs qemu/virt is described as using semi-hosting, therefore this change
should be orthogonal to existing assumptions while giving possibility to
store both bl1 and fip in FLASH0 at some point (additional changes required
for that).
Signed-off-by: Radoslaw Biernacki <radoslaw.biernacki@linaro.org>
Change-Id: I782bc3637c91c01eaee680b3c5c408e24b4b6e28
show more ...
|
| 558a6f44 | 17-May-2018 |
Radoslaw Biernacki <radoslaw.biernacki@linaro.org> |
qemu/qemu_sbsa: Adding Qemu SBSA platform
This patch introduces Qemu SBSA platform.
Both platform specific files where copied from qemu/qemu with changes for
DRAM base above 32bit and removal of ARM
qemu/qemu_sbsa: Adding Qemu SBSA platform
This patch introduces Qemu SBSA platform.
Both platform specific files where copied from qemu/qemu with changes for
DRAM base above 32bit and removal of ARMv7 conditional defines/code.
Documentation is aligned to rest of SBSA patches along the series and
planed changes in edk2-platform repo.
Fixes ARM-software/tf-issues#602
Signed-off-by: Radoslaw Biernacki <radoslaw.biernacki@linaro.org>
Change-Id: I8ebc34eedb2268365e479ef05654b2df1b99128c
show more ...
|
| a4668c36 | 16-Sep-2019 |
Artsem Artsemenka <artsem.artsemenka@arm.com> |
Cortex_hercules: Add support for Hercules-AE
Not tested on FVP Model.
Change-Id: Iedebc5c1fbc7ea577e94142b7feafa5546f1f4f9
Signed-off-by: Artsem Artsemenka <artsem.artsemenka@arm.com> |