1 /* 2 * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <arch_helpers.h> 9 #include <assert.h> 10 #include <common/bl_common.h> 11 #include <lib/el3_runtime/context_mgmt.h> 12 #include <common/debug.h> 13 #include <errno.h> 14 #include <mce.h> 15 #include <memctrl.h> 16 #include <common/runtime_svc.h> 17 #include <tegra_private.h> 18 19 extern uint32_t tegra186_system_powerdn_state; 20 21 /******************************************************************************* 22 * Tegra186 SiP SMCs 23 ******************************************************************************/ 24 #define TEGRA_SIP_NEW_VIDEOMEM_REGION 0x82000003 25 #define TEGRA_SIP_SYSTEM_SHUTDOWN_STATE 0x82FFFE01 26 #define TEGRA_SIP_MCE_CMD_ENTER_CSTATE 0x82FFFF00 27 #define TEGRA_SIP_MCE_CMD_UPDATE_CSTATE_INFO 0x82FFFF01 28 #define TEGRA_SIP_MCE_CMD_UPDATE_CROSSOVER_TIME 0x82FFFF02 29 #define TEGRA_SIP_MCE_CMD_READ_CSTATE_STATS 0x82FFFF03 30 #define TEGRA_SIP_MCE_CMD_WRITE_CSTATE_STATS 0x82FFFF04 31 #define TEGRA_SIP_MCE_CMD_IS_SC7_ALLOWED 0x82FFFF05 32 #define TEGRA_SIP_MCE_CMD_ONLINE_CORE 0x82FFFF06 33 #define TEGRA_SIP_MCE_CMD_CC3_CTRL 0x82FFFF07 34 #define TEGRA_SIP_MCE_CMD_ECHO_DATA 0x82FFFF08 35 #define TEGRA_SIP_MCE_CMD_READ_VERSIONS 0x82FFFF09 36 #define TEGRA_SIP_MCE_CMD_ENUM_FEATURES 0x82FFFF0A 37 #define TEGRA_SIP_MCE_CMD_ROC_FLUSH_CACHE_TRBITS 0x82FFFF0B 38 #define TEGRA_SIP_MCE_CMD_ENUM_READ_MCA 0x82FFFF0C 39 #define TEGRA_SIP_MCE_CMD_ENUM_WRITE_MCA 0x82FFFF0D 40 #define TEGRA_SIP_MCE_CMD_ROC_FLUSH_CACHE 0x82FFFF0E 41 #define TEGRA_SIP_MCE_CMD_ROC_CLEAN_CACHE 0x82FFFF0F 42 #define TEGRA_SIP_MCE_CMD_ENABLE_LATIC 0x82FFFF10 43 #define TEGRA_SIP_MCE_CMD_UNCORE_PERFMON_REQ 0x82FFFF11 44 #define TEGRA_SIP_MCE_CMD_MISC_CCPLEX 0x82FFFF12 45 46 /******************************************************************************* 47 * This function is responsible for handling all T186 SiP calls 48 ******************************************************************************/ 49 int plat_sip_handler(uint32_t smc_fid, 50 uint64_t x1, 51 uint64_t x2, 52 uint64_t x3, 53 uint64_t x4, 54 void *cookie, 55 void *handle, 56 uint64_t flags) 57 { 58 int mce_ret; 59 60 switch (smc_fid) { 61 62 /* 63 * Micro Coded Engine (MCE) commands reside in the 0x82FFFF00 - 64 * 0x82FFFFFF SiP SMC space 65 */ 66 case TEGRA_SIP_MCE_CMD_ENTER_CSTATE: 67 case TEGRA_SIP_MCE_CMD_UPDATE_CSTATE_INFO: 68 case TEGRA_SIP_MCE_CMD_UPDATE_CROSSOVER_TIME: 69 case TEGRA_SIP_MCE_CMD_READ_CSTATE_STATS: 70 case TEGRA_SIP_MCE_CMD_WRITE_CSTATE_STATS: 71 case TEGRA_SIP_MCE_CMD_IS_SC7_ALLOWED: 72 case TEGRA_SIP_MCE_CMD_CC3_CTRL: 73 case TEGRA_SIP_MCE_CMD_ECHO_DATA: 74 case TEGRA_SIP_MCE_CMD_READ_VERSIONS: 75 case TEGRA_SIP_MCE_CMD_ENUM_FEATURES: 76 case TEGRA_SIP_MCE_CMD_ROC_FLUSH_CACHE_TRBITS: 77 case TEGRA_SIP_MCE_CMD_ENUM_READ_MCA: 78 case TEGRA_SIP_MCE_CMD_ENUM_WRITE_MCA: 79 case TEGRA_SIP_MCE_CMD_ROC_FLUSH_CACHE: 80 case TEGRA_SIP_MCE_CMD_ROC_CLEAN_CACHE: 81 case TEGRA_SIP_MCE_CMD_ENABLE_LATIC: 82 case TEGRA_SIP_MCE_CMD_UNCORE_PERFMON_REQ: 83 case TEGRA_SIP_MCE_CMD_MISC_CCPLEX: 84 85 /* clean up the high bits */ 86 smc_fid &= MCE_CMD_MASK; 87 88 /* execute the command and store the result */ 89 mce_ret = mce_command_handler(smc_fid, x1, x2, x3); 90 write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X0, mce_ret); 91 92 return 0; 93 94 case TEGRA_SIP_SYSTEM_SHUTDOWN_STATE: 95 96 /* clean up the high bits */ 97 x1 = (uint32_t)x1; 98 99 /* 100 * SC8 is a special Tegra186 system state where the CPUs and 101 * DRAM are powered down but the other subsystem is still 102 * alive. 103 */ 104 105 return 0; 106 107 default: 108 break; 109 } 110 111 return -ENOTSUP; 112 } 113