1 /* 2 * Copyright (c) 2019, MediaTek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <arch_helpers.h> 9 #include <common/bl_common.h> 10 #include <common/desc_image_load.h> 11 #include <devapc.h> 12 #include <plat/common/common_def.h> 13 #include <drivers/console.h> 14 #include <common/debug.h> 15 #include <drivers/generic_delay_timer.h> 16 #include <mcucfg.h> 17 #include <mt_gic_v3.h> 18 #include <lib/coreboot.h> 19 #include <lib/mmio.h> 20 #include <mtk_mcdi.h> 21 #include <mtk_plat_common.h> 22 #include <mtspmc.h> 23 #include <plat_debug.h> 24 #include <plat_params.h> 25 #include <plat_private.h> 26 #include <platform_def.h> 27 #include <scu.h> 28 #include <spm.h> 29 #include <drivers/ti/uart/uart_16550.h> 30 31 static entry_point_info_t bl32_ep_info; 32 static entry_point_info_t bl33_ep_info; 33 34 static void platform_setup_cpu(void) 35 { 36 mmio_write_32((uintptr_t)&mt8183_mcucfg->mp0_rw_rsvd0, 0x00000001); 37 38 /* Mcusys dcm control */ 39 /* Enable pll plldiv dcm */ 40 mmio_setbits_32((uintptr_t)&mt8183_mcucfg->bus_pll_divider_cfg, 41 BUS_PLLDIV_DCM); 42 mmio_setbits_32((uintptr_t)&mt8183_mcucfg->mp0_pll_divider_cfg, 43 MP0_PLLDIV_DCM); 44 mmio_setbits_32((uintptr_t)&mt8183_mcucfg->mp2_pll_divider_cfg, 45 MP2_PLLDIV_DCM); 46 /* Enable mscib dcm */ 47 mmio_clrsetbits_32((uintptr_t)&mt8183_mcucfg->mscib_dcm_en, 48 MCSIB_CACTIVE_SEL_MASK, MCSIB_CACTIVE_SEL); 49 mmio_clrsetbits_32((uintptr_t)&mt8183_mcucfg->mscib_dcm_en, 50 MCSIB_DCM_MASK, MCSIB_DCM); 51 /* Enable adb400 dcm */ 52 mmio_clrsetbits_32((uintptr_t)&mt8183_mcucfg->cci_adb400_dcm_config, 53 CCI_ADB400_DCM_MASK, CCI_ADB400_DCM); 54 /* Enable bus clock dcm */ 55 mmio_setbits_32((uintptr_t)&mt8183_mcucfg->cci_clk_ctrl, 56 MCU_BUS_DCM); 57 /* Enable bus fabric dcm */ 58 mmio_clrsetbits_32( 59 (uintptr_t)&mt8183_mcucfg->mcusys_bus_fabric_dcm_ctrl, 60 MCUSYS_BUS_FABRIC_DCM_MASK, 61 MCUSYS_BUS_FABRIC_DCM); 62 /* Enable l2c sram dcm */ 63 mmio_setbits_32((uintptr_t)&mt8183_mcucfg->l2c_sram_ctrl, 64 L2C_SRAM_DCM); 65 /* Enable busmp0 sync dcm */ 66 mmio_clrsetbits_32((uintptr_t)&mt8183_mcucfg->sync_dcm_config, 67 SYNC_DCM_MASK, SYNC_DCM); 68 /* Enable cntvalue dcm */ 69 mmio_setbits_32((uintptr_t)&mt8183_mcucfg->mcu_misc_dcm_ctrl, 70 CNTVALUEB_DCM); 71 /* Enable dcm cluster stall */ 72 mmio_clrsetbits_32( 73 (uintptr_t)&mt8183_mcucfg->sync_dcm_cluster_config, 74 MCUSYS_MAX_ACCESS_LATENCY_MASK, 75 MCUSYS_MAX_ACCESS_LATENCY); 76 mmio_setbits_32((uintptr_t)&mt8183_mcucfg->sync_dcm_cluster_config, 77 MCU0_SYNC_DCM_STALL_WR_EN); 78 /* Enable rgu dcm */ 79 mmio_setbits_32((uintptr_t)&mt8183_mcucfg->mp0_rgu_dcm_config, 80 CPUSYS_RGU_DCM_CINFIG); 81 } 82 83 /******************************************************************************* 84 * Return a pointer to the 'entry_point_info' structure of the next image for 85 * the security state specified. BL33 corresponds to the non-secure image type 86 * while BL32 corresponds to the secure image type. A NULL pointer is returned 87 * if the image does not exist. 88 ******************************************************************************/ 89 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 90 { 91 entry_point_info_t *next_image_info; 92 93 next_image_info = (type == NON_SECURE) ? &bl33_ep_info : &bl32_ep_info; 94 assert(next_image_info->h.type == PARAM_EP); 95 96 /* None of the images on this platform can have 0x0 as the entrypoint */ 97 if (next_image_info->pc) 98 return next_image_info; 99 else 100 return NULL; 101 } 102 103 /******************************************************************************* 104 * Perform any BL31 early platform setup. Here is an opportunity to copy 105 * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they 106 * are lost (potentially). This needs to be done before the MMU is initialized 107 * so that the memory layout can be used while creating page tables. 108 * BL2 has flushed this information to memory, so we are guaranteed to pick up 109 * good data. 110 ******************************************************************************/ 111 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 112 u_register_t arg2, u_register_t arg3) 113 { 114 static console_16550_t console; 115 116 params_early_setup(arg1); 117 118 #if COREBOOT 119 if (coreboot_serial.type) 120 console_16550_register(coreboot_serial.baseaddr, 121 coreboot_serial.input_hertz, 122 coreboot_serial.baud, 123 &console); 124 #else 125 console_16550_register(UART0_BASE, UART_CLOCK, UART_BAUDRATE, &console); 126 #endif 127 128 NOTICE("MT8183 bl31_setup\n"); 129 130 bl31_params_parse_helper(arg0, &bl32_ep_info, &bl33_ep_info); 131 } 132 133 134 /******************************************************************************* 135 * Perform any BL31 platform setup code 136 ******************************************************************************/ 137 void bl31_platform_setup(void) 138 { 139 devapc_init(); 140 141 platform_setup_cpu(); 142 generic_delay_timer_init(); 143 144 /* Initialize the GIC driver, CPU and distributor interfaces */ 145 mt_gic_driver_init(); 146 mt_gic_init(); 147 148 /* Init mcsi SF */ 149 plat_mtk_cci_init_sf(); 150 151 #if SPMC_MODE == 1 152 spmc_init(); 153 #endif 154 spm_boot_init(); 155 mcdi_init(); 156 } 157 158 /******************************************************************************* 159 * Perform the very early platform specific architectural setup here. At the 160 * moment this is only intializes the mmu in a quick and dirty way. 161 ******************************************************************************/ 162 void bl31_plat_arch_setup(void) 163 { 164 plat_mtk_cci_init(); 165 plat_mtk_cci_enable(); 166 167 enable_scu(read_mpidr()); 168 169 plat_configure_mmu_el3(BL_CODE_BASE, 170 BL_COHERENT_RAM_END - BL_CODE_BASE, 171 BL_CODE_BASE, 172 BL_CODE_END, 173 BL_COHERENT_RAM_BASE, 174 BL_COHERENT_RAM_END); 175 } 176