Tegra194: sip_calls: mark unused parameter as const

This patch marks the unused parameter 'cookie', to the
plat_sip_handler() function, as const to fix an issue
flagged by the MISRA scan.

Change-Id

Tegra194: sip_calls: mark unused parameter as const

This patch marks the unused parameter 'cookie', to the
plat_sip_handler() function, as const to fix an issue
flagged by the MISRA scan.

Change-Id: I53fdd2caadf43fef17fbc3a50a18bf7fdbd42d39
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra194: implement handler to retrieve power domain tree

This patch implements the platform handler to return the pointer
to the power domain tree.

Change-Id: I74ea7002c7a461a028b4a252bbd354256fdc

Tegra194: implement handler to retrieve power domain tree

This patch implements the platform handler to return the pointer
to the power domain tree.

Change-Id: I74ea7002c7a461a028b4a252bbd354256fdc0647
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra194: mce: fix function declaration conflicts

To fix MISRA defects, remove union in t186 MCE drivers
this driver should compatible with that.

Change-Id: I09e96a1874dd86626c7e41c92a1484a84e38740

Tegra194: mce: fix function declaration conflicts

To fix MISRA defects, remove union in t186 MCE drivers
this driver should compatible with that.

Change-Id: I09e96a1874dd86626c7e41c92a1484a84e387402
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>

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Tegra194: add macros to read GPU reset status

This patch adds macros to check the GPU reset status bit, before
resizing the VideoMem region.

Change-Id: I4377c1ce1ac6d3bd14c7db83526b99d72bdb41ed
Sig

Tegra194: add macros to read GPU reset status

This patch adds macros to check the GPU reset status bit, before
resizing the VideoMem region.

Change-Id: I4377c1ce1ac6d3bd14c7db83526b99d72bdb41ed
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra194: skip notifying MCE in fake system suspend

- In pre-silicon platforms, MCE might not be ready
to support system suspend(SC7)
- Thus, in fake system suspend mode, bypass waiting for
MCE'

Tegra194: skip notifying MCE in fake system suspend

- In pre-silicon platforms, MCE might not be ready
to support system suspend(SC7)
- Thus, in fake system suspend mode, bypass waiting for
MCE's acknowledgment to enter system suspend

Change-Id: Ia3c010ce080c4283ab1233ba82e3e577adca34f6
Signed-off-by: Vignesh Radhakrishnan <vigneshr@nvidia.com>

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Tegra194: Enable system suspend

This patch does the following:
1. Populate the cstate info corresponding to system suspend
and communicate it to the MCE
2. Ask for MCE's acknowledgement for enter

Tegra194: Enable system suspend

This patch does the following:
1. Populate the cstate info corresponding to system suspend
and communicate it to the MCE
2. Ask for MCE's acknowledgement for entering system suspend
and instruct MCE to get inside system suspend once
permitted

Change-Id: I51e1910e24a7e61e36ac2d12ce271290e433e506
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Signed-off-by: Vignesh Radhakrishnan <vigneshr@nvidia.com>

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Merge changes from topic "tegra-downstream-092319" into integration

* changes:
Tegra194: add macros for security carveout configuration registers
Tegra194: add 'TEGRA_TMRUS_SIZE' macro
Tegra19

Merge changes from topic "tegra-downstream-092319" into integration

* changes:
Tegra194: add macros for security carveout configuration registers
Tegra194: add 'TEGRA_TMRUS_SIZE' macro
Tegra194: Fix TEGRA186_SMMU_CTX_SIZE
Tegra194: Dont run MCE firmware on Emulation
Tegra194: remove GPU, MPCORE and PTC registers from streamid list
Tegra194: Support SMC64 encoding for MCE calls
Tegra194: Enable MCE driver
Tegra194: enable SMMU
Tegra194: add support for multiple SMMU devices
Tegra194: add SMMU and mc_sid support
Tegra194: psci: support for 64-bit TZDRAM base
Tegra194: base commit for the platform
Revert "Tegra: Add support for fake system suspend"

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Merge "plat/arm: Re-enable PIE when RESET_TO_BL31=1" into integration

n1sdp: setup multichip gic routing table

N1SDP supports multichip configuration wherein n1sdp boards are
connected over high speed coherent CCIX link, for now only dual-chip
is supported.

Whether o

n1sdp: setup multichip gic routing table

N1SDP supports multichip configuration wherein n1sdp boards are
connected over high speed coherent CCIX link, for now only dual-chip
is supported.

Whether or not multiple chips are present is dynamically probed by
SCP firmware and passed on to TF-A, routing table will be set up
only if multiple chips are present.

Initialize GIC-600 multichip operation by overriding the default GICR
frames with array of GICR frames and setting the chip 0 as routing
table owner.

Change-Id: Ida35672be4bbf4c517469a5b330548d75e593ff2
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>

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plat/arm: Re-enable PIE when RESET_TO_BL31=1

Earlier PIE support was enabled for all arm platforms when
RESET_TO_BL31=1, but later on it was restricted only to FVP with patch
SHA d4580d17 because of

plat/arm: Re-enable PIE when RESET_TO_BL31=1

Earlier PIE support was enabled for all arm platforms when
RESET_TO_BL31=1, but later on it was restricted only to FVP with patch
SHA d4580d17 because of n1sdp platform.

Now it has been verified that PIE does work for n1sdp platform also, so
enabling it again for all arm platforms.

Change-Id: I05ad4f1775ef72e7cb578ec9245cde3fbce971a5
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>

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plat: imx: Correct the SGIs that used for secure interrupt

Normally, SGI6 & SGI7 is used by non-secure world, these
two SGIs should not be reserved for secure interrupt purpose.
On i.MX8M platform,

plat: imx: Correct the SGIs that used for secure interrupt

Normally, SGI6 & SGI7 is used by non-secure world, these
two SGIs should not be reserved for secure interrupt purpose.
On i.MX8M platform, SGI8 is used for secure group0 IPI for
DDR DVFS, So update the code to reserve SGI8 for secure world.

Change-Id: Ib1ed9786e0a79bb729b120a0d4d791d13b6f048a
Signed-off-by: Jacky Bai <ping.bai@nxp.com>

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mediatek: mt8183: switch PLL/CLKSQ/ck_off/axi_26m control to SPM

1. Switch ARMPLL_LL/CCIPLL/MAINPLL/MPLL control to SPM
2. Switch CLKSQ1/TDCLKSQ control to SPM
3. Switch ck_off/axi_26m control to SP

mediatek: mt8183: switch PLL/CLKSQ/ck_off/axi_26m control to SPM

1. Switch ARMPLL_LL/CCIPLL/MAINPLL/MPLL control to SPM
2. Switch CLKSQ1/TDCLKSQ control to SPM
3. Switch ck_off/axi_26m control to SPM

BUG=b:136980838
TEST=system suspend/resume passed

Change-Id: I5c8506f7cf16d5cdaeb5ef8caa60a2992a361e18
Signed-off-by: Roger Lu <roger.lu@mediatek.com>

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plat: imx8mm: Add the support for opteed spd on imx8mq/imx8mm

Add the basic support for opteed SPD on imx8mq & imx8mm.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I6c4855c89dea78d13d172c

plat: imx8mm: Add the support for opteed spd on imx8mq/imx8mm

Add the basic support for opteed SPD on imx8mq & imx8mm.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I6c4855c89dea78d13d172c3d86cf047f829e51ce

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plat/arm/gicv3: add support for probing multiple GIC Redistributor frames

ARM platform can have a non-contiguous GICR frames. For instance, a
multi socket platform can have two or more GIC Redistrib

plat/arm/gicv3: add support for probing multiple GIC Redistributor frames

ARM platform can have a non-contiguous GICR frames. For instance, a
multi socket platform can have two or more GIC Redistributor frames
which are 4TB apart. Hence it is necessary for the `gicv3_rdistif_probe`
function to probe all the GICR frames available in the platform.

Introduce `plat_arm_override_gicr_frames` function which platforms can
use to override the default gicr_frames which holds the GICR base
address of the primary cpu.

Change-Id: I1f537b0d871a679cb256092944737f2e55ab866e
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>

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n1sdp: update platform macros for dual-chip setup

N1SDP supports multichip configuration wherein n1sdp boards are
connected over high speed coherent CCIX link for now only dual-chip is
supported.

n1sdp: update platform macros for dual-chip setup

N1SDP supports multichip configuration wherein n1sdp boards are
connected over high speed coherent CCIX link for now only dual-chip is
supported.

A single instance of TF-A runs on master chip which should be aware of
slave chip's CPU and memory topology.

This patch updates platform macros to include remote chip's information
and also ensures that a single version of firmware works for both single
and dual-chip setup.

Change-Id: I75799fd46dc10527aa99585226099d836c21da70
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>

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n1sdp: introduce platform information SDS region

Platform information structure holds information about platform's DDR
size(local/remote) which will be used to zero out the memory before
enabling th

n1sdp: introduce platform information SDS region

Platform information structure holds information about platform's DDR
size(local/remote) which will be used to zero out the memory before
enabling the ECC capability as well as information about multichip
setup. Multichip and remote DDR information can only be probed in SCP,
SDS region will be used by TF-A to get this information at boot up.

This patch introduces a new SDS to store platform information, which is
populated dynamically by SCP Firmware.previously used mem_info SDS is
also made part of this structure itself.

The platform information is also passed to BL33 by copying it to Non-
Secure SRAM.

Change-Id: I4781dc6a7232c3c0a3219b164d943ce9e3e469ee
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>

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ti: k3: common: Add PIE support

Running TF-A from non-standard location such as DRAM is useful for some
SRAM heavy use-cases. Allow the TF-A binary to be executed from an
arbitrary memory location.

ti: k3: common: Add PIE support

Running TF-A from non-standard location such as DRAM is useful for some
SRAM heavy use-cases. Allow the TF-A binary to be executed from an
arbitrary memory location.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Change-Id: Icd97926e4d97f37d7cde4a92758a52f57d569111

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Tegra194: add macros for security carveout configuration registers

This patch adds macros defining the generalised security carveout
registers. These macros help us program the TZRAM carveout access

Tegra194: add macros for security carveout configuration registers

This patch adds macros defining the generalised security carveout
registers. These macros help us program the TZRAM carveout access
and the Video Protect Clear carveout access.

Change-Id: I8f7b24b653fdb702fb57a4097801cb3eae050294
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra194: add 'TEGRA_TMRUS_SIZE' macro

This patch defines the macro for the TEGRA_TMRUS aperture size.

Change-Id: I33fb674c6a7be8d02971667e7bf8650b7adc62ef
Signed-off-by: Steven Kao <skao@nvidia.co

Tegra194: add 'TEGRA_TMRUS_SIZE' macro

This patch defines the macro for the TEGRA_TMRUS aperture size.

Change-Id: I33fb674c6a7be8d02971667e7bf8650b7adc62ef
Signed-off-by: Steven Kao <skao@nvidia.com>

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Tegra194: Fix TEGRA186_SMMU_CTX_SIZE

TEGRA186_SMMU_CTX_SIZE should match the numbe of elements
in smmu_ctx_regs, which is defined in smmu_plat_config.h.
The current number of elements are 0x490.

Ch

Tegra194: Fix TEGRA186_SMMU_CTX_SIZE

TEGRA186_SMMU_CTX_SIZE should match the numbe of elements
in smmu_ctx_regs, which is defined in smmu_plat_config.h.
The current number of elements are 0x490.

Change-Id: If0614ea8ef8b6a8f5da1a3279abaf9255eb76420
Signed-off-by: Stefan Kristiansson <stefank@nvidia.com>

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Tegra194: Dont run MCE firmware on Emulation

Dont run MCE firmware on pre-silicon emulation platforms

Change-Id: I2a8d653e46f494621580ca92271a18e62f648859
Signed-off-by: Rohit Khanna <rokhanna@nvid

Tegra194: Dont run MCE firmware on Emulation

Dont run MCE firmware on pre-silicon emulation platforms

Change-Id: I2a8d653e46f494621580ca92271a18e62f648859
Signed-off-by: Rohit Khanna <rokhanna@nvidia.com>

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Tegra194: remove GPU, MPCORE and PTC registers from streamid list

GPU, MPCORE and PTC clients are changed and not going through SMMU.
Removing it from streamid list.

Change-Id: I14b450a11f02ad6c1a9

Tegra194: remove GPU, MPCORE and PTC registers from streamid list

GPU, MPCORE and PTC clients are changed and not going through SMMU.
Removing it from streamid list.

Change-Id: I14b450a11f02ad6c1a97e67e487d6d624911d019
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>

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Tegra194: Support SMC64 encoding for MCE calls

This patch uses SMC64 encoding for all MCE SMC calls originating
from the linux kernel.

Change-Id: Ic4633de5c638566012db033bbaf8c9d9343acdc0
Signed-of

Tegra194: Support SMC64 encoding for MCE calls

This patch uses SMC64 encoding for all MCE SMC calls originating
from the linux kernel.

Change-Id: Ic4633de5c638566012db033bbaf8c9d9343acdc0
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra194: Enable MCE driver

This patch enable MCE driver for T19x SoC. The MCE driver
takes care of the communication with the MCE firmware to
achieve:

- Cold boot
- Warm boot
- Core/Cluster/System

Tegra194: Enable MCE driver

This patch enable MCE driver for T19x SoC. The MCE driver
takes care of the communication with the MCE firmware to
achieve:

- Cold boot
- Warm boot
- Core/Cluster/System Power management
- Custom MCE requests

Change-Id: I75854c0b649a691e9b244d9ed9fc1c19743e3e8d
Signed-off-by: Steven Kao <skao@nvidia.com>

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Tegra194: enable SMMU

Enable smmu by setting ENABLE_SMMU_DEVICE to 1.

Change-Id: I9135071b257a166fa6082b7fe409bcd315cf6838
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>