feat(mt8196): add CPU QoS stub implementation

Add stub implementation for CPU QoS driver.

Change-Id: I1296aaff34c860ac878ad2ac26b511fb2411510e
Signed-off-by: Yidi Lin <yidilin@chromium.org>

refactor(mediatek): update EMI stub implementation

Refactor EMI stub implementation with following changes.
- Move the SiP call handlers to TF-A upstream.
- Move EMI definition used by APUSYS to pla

refactor(mediatek): update EMI stub implementation

Refactor EMI stub implementation with following changes.
- Move the SiP call handlers to TF-A upstream.
- Move EMI definition used by APUSYS to platform_def.h.
- Remove CONFIG_MTK_APUSYS_EMI_SUPPORT.

Change-Id: I30e1ee7f2ea2d6dc3415adba91cbe310af9b5eeb
Signed-off-by: Yidi Lin <yidilin@chromium.org>

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feat(mediatek): add APIs exposed to the static library

To decrease the static library's dependency on TF-A, add API wrappers
for mmap_add_dynamic_region and mmap_remove_dynamic_region.
mtk_bl31_map_

feat(mediatek): add APIs exposed to the static library

To decrease the static library's dependency on TF-A, add API wrappers
for mmap_add_dynamic_region and mmap_remove_dynamic_region.
mtk_bl31_map_to_sip_error is also added for translating mtk_bl31_status
codes to their corresponding MKT_SIP_E* error codes.

Change-Id: Ib4a3593ee8b481b076430d054c08f33cc3b2fa08
Signed-off-by: Yidi Lin <yidilin@chromium.org>

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feat(mt8196): add MMinfra support

Add MMinfra support for MT8196.

Change-Id: I5504764d05fecace4f0d3981785ff1bc8ae13d00
Signed-off-by: Yidi Lin <yidilin@chromium.org>

feat(mt8196): add UFS functions used by the static library

Those functions are used by the static library. To reduce the
proprietary code's reliance on other drivers, these functions should be
moved

feat(mt8196): add UFS functions used by the static library

Those functions are used by the static library. To reduce the
proprietary code's reliance on other drivers, these functions should be
moved to the upstream repository.

Change-Id: I6a9430c24bb1f9c1d473b43e65168b620e6bd6b9
Signed-off-by: Yidi Lin <yidilin@chromium.org>

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fix(fvp): increase EventLog size for OP-TEE with multiple SPs

When OP-TEE runs with multiple Secure Partitions (SPs), a larger
EventLog size is required to accommodate the additional measurements.
T

fix(fvp): increase EventLog size for OP-TEE with multiple SPs

When OP-TEE runs with multiple Secure Partitions (SPs), a larger
EventLog size is required to accommodate the additional measurements.
This patch updates the configuration to allocate sufficient memory
in such cases.

In the future, the Maximum EventLog size should be calculated based
on the maximum number of images loaded by BL2. That enhancement can
be addressed in a separate patch.

Change-Id: Ibd9bed0a5b1029158142711fd08809729dd05b08
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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fix(intel): support SMC 64bit return args in SiPSVC V3

Update SiPSVC V3 framework to support 64bit SMC return
arguments and other miscellaneous debug prints.

Change-Id: I659a0aea8e24eb5876e69327e44

fix(intel): support SMC 64bit return args in SiPSVC V3

Update SiPSVC V3 framework to support 64bit SMC return
arguments and other miscellaneous debug prints.

Change-Id: I659a0aea8e24eb5876e69327e44a667d2a54c241
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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fix(intel): verify data size in AES GCM and GCM-GHASH modes

On the Agilex5 platform, in the FCS AES GCM and GCM-GHASH
modes enc/dec data size should be 0 or multiple of 16bytes.

Change-Id: I23e51bf

fix(intel): verify data size in AES GCM and GCM-GHASH modes

On the Agilex5 platform, in the FCS AES GCM and GCM-GHASH
modes enc/dec data size should be 0 or multiple of 16bytes.

Change-Id: I23e51bf942771e74d16f8a87fbfdbf36ef3c3893
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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fix(intel): update FCS AES method for GCM block modes

On the Agilex5 platform, AES enc/dec with GCM and GCM-GHASH
modes, the source and destination size should be in multiples
of 16 bytes. For other

fix(intel): update FCS AES method for GCM block modes

On the Agilex5 platform, AES enc/dec with GCM and GCM-GHASH
modes, the source and destination size should be in multiples
of 16 bytes. For other platforms and other modes, it should
be in multiples of 32 bytes.

Change-Id: I0fa9adafb5d7fc4c794a4acb9339cf8259df0c78
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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fix(intel): update initialization to prevent warnings message

This patch is used to solve TF-A build warning with build option
ENABLE_LTO=1

Change-Id: Id427e9d6f96e21fc132fb5af60e9499e1bbecea3
Sign

fix(intel): update initialization to prevent warnings message

This patch is used to solve TF-A build warning with build option
ENABLE_LTO=1

Change-Id: Id427e9d6f96e21fc132fb5af60e9499e1bbecea3
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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feat(intel): update CPUECTLR_EL1 to boost ethernet performance

This patch is the workaround for Agilex5 Ethernet for performance
boost.

Change-Id: I702f0cb0beff8b3ea119205ec41dd4e825e9126b
Signed-o

feat(intel): update CPUECTLR_EL1 to boost ethernet performance

This patch is the workaround for Agilex5 Ethernet for performance
boost.

Change-Id: I702f0cb0beff8b3ea119205ec41dd4e825e9126b
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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fix(allwinner): fix variable may be used uninitialized error

When building with LTO, the compiler observes that i2c_read() can return
without writing val, declaring the variable may be used unnitial

fix(allwinner): fix variable may be used uninitialized error

When building with LTO, the compiler observes that i2c_read() can return
without writing val, declaring the variable may be used unnitialized.
However, there is a sufficient error check that will prevent an actual
use. So calm the compiler by giving a safe default.

Change-Id: I558618467ae324a6b5b495ec9d204935135f226d
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(lx2160): set snoop-delayed exclusive handling on A72 cores

Snoop requests should not be responded to during atomic operations. This
can be handled by the interconnect using its global monitor or

fix(lx2160): set snoop-delayed exclusive handling on A72 cores

Snoop requests should not be responded to during atomic operations. This
can be handled by the interconnect using its global monitor or by the
core's SCU delaying to check for the corresponding atomic monitor state.

Similar to commit 5668db72b ("feat(ti): set snoop-delayed exclusive
handling on A72 cores") enable the snoop-delayed exclusive handling
bit to inform the core it needs to delay responses to perform this check.

Change-Id: I984f3d08b7a608f59f38e01461aeb448f2ef5af1
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>

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feat(mt8189): add IOMMU enable control in SiP service

Add SiP service for multimedia & infra master to enable/disable
MM & INFRA IOMMU in secure world

Signed-off-by: Friday Yang <friday.yang@mediat

feat(mt8189): add IOMMU enable control in SiP service

Add SiP service for multimedia & infra master to enable/disable
MM & INFRA IOMMU in secure world

Signed-off-by: Friday Yang <friday.yang@mediatek.corp-partner.google.com>
Change-Id: I90b4843731968671b89e3062872e1cd9aec52370

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fix(lx2160): add DDRC missing DIMMs

LX2160a has 2 DDRC. Let's assume 2 DIMMs.

Without such modification, only half of the memory if available on the
board.

Inspired from plat/nxp/soc-lx2160a/lx216

fix(lx2160): add DDRC missing DIMMs

LX2160a has 2 DDRC. Let's assume 2 DIMMs.

Without such modification, only half of the memory if available on the
board.

Inspired from plat/nxp/soc-lx2160a/lx2160ardb/platform.mk

Change-Id: Iea4c11de104a2999fdff0da7f8e7a3baada0fd3d
Signed-off-by: Vincent Jardin <vjardin@free.fr>

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feat(smcc): introduce a new vendor_el3 service for ACS SMC handler

In preparation to add support for the Architecture Compliance Suite
SMC services, reserve a SMC ID and introduce a handler function

feat(smcc): introduce a new vendor_el3 service for ACS SMC handler

In preparation to add support for the Architecture Compliance Suite
SMC services, reserve a SMC ID and introduce a handler function.
Currently, an empty placeholder function is added and future support
will be introduced for the handler support.

More info on System ACS, please refer below link,
https://developer.arm.com/Architectures/Architectural%20Compliance%20Suite

Signed-off-by: Nandan J <Nandan.J@arm.com>
Change-Id: Ib13ccae9d3829e3dcd1cd33c4a7f27efe1436d03

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fix(stm32mp2): correct typo in definition header

Fix a typo about the platform in a comment (STM32MP2 instead
of STM32MP1).

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Change-I

fix(stm32mp2): correct typo in definition header

Fix a typo about the platform in a comment (STM32MP2 instead
of STM32MP1).

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Change-Id: I6a58b659d97d7143e277dea57d4eede7729092bc

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feat(versal): add hooks for mmap and early setup

Add early setup hooks through custom_early_setup() and provide a
mechanism to support custom memory mapping, including the extension
of the memory ma

feat(versal): add hooks for mmap and early setup

Add early setup hooks through custom_early_setup() and provide a
mechanism to support custom memory mapping, including the extension
of the memory map via custom_mmap_add(). This change may also
require alignment of the MAX_XLAT_TABLE and MAX_XLAT_TABLES macros.
These can be defined within the custom_pkg.mk makefile as follows:

MAX_MMAP_REGIONS := XY
$(eval $(call add_define,MAX_MMAP_REGIONS))
MAX_XLAT_TABLES := XZ
$(eval $(call add_define,MAX_XLAT_TABLES))

If PLATFORM_STACK_SIZE is not already defined, a default value
should be used. This allows for configurability of the stack size
across different interfaces, such as custom packages. The
custom_early_setup() function enables early low-level operations
to bring the system into a correct state. Support for a custom
SiP service is also added. A basic implementation of
custom_smc_handler() is provided by the platform, while the actual
definition is expected to be supplied by the custom package. This
feature is designed for use by external libraries, such as those
that require status checking. This code introduces a generic
framework for integrating custom logic via the
$(CUSTOM_PKG_PATH)/custom_pkg.mk makefile, including
optional support for custom SMC functionality, which is determined
by the custom package.

Change-Id: If9107b32c8c1ca4026d0a2980901e841fc6e03f7
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>

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Merge changes from topic "psa_key_id_mgmt" into integration

* changes:
feat(auth): extend REGISTER_CRYPTO_LIB calls
feat(bl): adding psa crypto - crypto_mod_finish()
feat(fvp): increase BL1 RW

Merge changes from topic "psa_key_id_mgmt" into integration

* changes:
feat(auth): extend REGISTER_CRYPTO_LIB calls
feat(bl): adding psa crypto - crypto_mod_finish()
feat(fvp): increase BL1 RW for PSA Crypto
feat(auth): mbedtls psa key id mgmt
feat(auth): add crypto_mod_finish() function
feat(auth): add update of current_pk_oid in auth
feat(auth): add util file for current pk_oid
feat(auth): increase mbedtls heap for PSA RSA
feat(auth): introducing auth.mk

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feat(auth): extend REGISTER_CRYPTO_LIB calls

Extend REGISTER_CRYPTO_LIB calls with NULL to allow for
the addition of the cryto_mod_finish() function.

Signed-off-by: Lauren Wehrmeister <lauren.wehrm

feat(auth): extend REGISTER_CRYPTO_LIB calls

Extend REGISTER_CRYPTO_LIB calls with NULL to allow for
the addition of the cryto_mod_finish() function.

Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: If41ed1be50e1d98b42b266c7905269f142bb67c7

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feat(fvp): increase BL1 RW for PSA Crypto

Increase BL1 RW for PSA Crypto due to PSA key ID management redesign
needing an increase in heap size.

Signed-off-by: Lauren Wehrmeister <lauren.wehrmeiste

feat(fvp): increase BL1 RW for PSA Crypto

Increase BL1 RW for PSA Crypto due to PSA key ID management redesign
needing an increase in heap size.

Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: I7c8d009f244be6252eff0d3ded3f1ca83fb1de21

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feat(auth): introducing auth.mk

Introducing authentication specific makefile auth.mk to include common
auth source files.

Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: I

feat(auth): introducing auth.mk

Introducing authentication specific makefile auth.mk to include common
auth source files.

Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: Ifb07c48861fe415d82cb7390c3a5f6e60ba699d9

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Merge changes from topic "refactor_eip76_driver" into integration

* changes:
feat(marvell): add trng driver
revert(rambus-trng): remove ip-76 driver

feat(marvell): add trng driver

Armada-7K/8K and CN913x integrated the Rambus EIP-97 IP on CP11x die. It
supports to generate up to 4 32-bit random number in one shot.

This trivial driver provisions

feat(marvell): add trng driver

Armada-7K/8K and CN913x integrated the Rambus EIP-97 IP on CP11x die. It
supports to generate up to 4 32-bit random number in one shot.

This trivial driver provisions a simple API to read the random numbers
from hardware. It allows the bootloader to get one 32-bit or 64-bit
random number via SMC call to support KASLR.

Change-Id: I1707a85512ca163b8c7ab1644ff0f7e2fcf57344
Signed-off-by: Wilson Ding <dingwei@marvell.com>

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Merge "fix(imx93): trdc: restrict BLK_CTRL_S_AONMIX to secure world" into integration