Merge "zynqmp: pm_service: Add support to query max divisor" into integration

Merge "rpi3/4: Add support for offlining CPUs" into integration

stm32mp1: Add support for SPI-NOR boot device

STM32MP1 platform is able to boot from SPI-NOR devices.
These modifications add this support using the new
SPI-NOR framework.

Change-Id: I75ff9eba4661f

stm32mp1: Add support for SPI-NOR boot device

STM32MP1 platform is able to boot from SPI-NOR devices.
These modifications add this support using the new
SPI-NOR framework.

Change-Id: I75ff9eba4661f9fb87ce24ced2bacbf8558ebe44
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>

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stm32mp1: Add support for SPI-NAND boot device

STM32MP1 platform is able to boot from SPI-NAND devices.
These modifications add this support using the new
SPI-NAND framework.

Change-Id: I0d5448bdc4

stm32mp1: Add support for SPI-NAND boot device

STM32MP1 platform is able to boot from SPI-NAND devices.
These modifications add this support using the new
SPI-NAND framework.

Change-Id: I0d5448bdc4bde153c1209e8043846c0f935ae5ba
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>

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stm32mp1: Add support for raw NAND boot device

STM32MP1 platform is able to boot from raw NAND devices.
These modifications add this support using the new
raw NAND framework.

Change-Id: I9e9c2b0393

stm32mp1: Add support for raw NAND boot device

STM32MP1 platform is able to boot from raw NAND devices.
These modifications add this support using the new
raw NAND framework.

Change-Id: I9e9c2b03930f98a5ac23f2b6b41945bef43e5043
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>

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stm32mp1: Reduce MAX_XLAT_TABLES to 4

For STM32MP1, the address space is 4GB, which can be first divided
in 4 parts of 1GB. This LVL1 table is already mapped regardless
of MAX_XLAT_TABLES.
Fixing ty

stm32mp1: Reduce MAX_XLAT_TABLES to 4

For STM32MP1, the address space is 4GB, which can be first divided
in 4 parts of 1GB. This LVL1 table is already mapped regardless
of MAX_XLAT_TABLES.
Fixing typo: Replace Ko to KB.

BL2/sp_min for platform STM32MP1 requires 4 MMU translation tables:
- a level2 table and a level3 table for identity mapped SYSRAM
- a level2 table mapping 2MB of BootROM runtime resources
- a level2 table mapping 2MB of secure DDR (case BL32 is OP-TEE)

Change-Id: If80cbd4fccc7689b39dd540d6649b1313557f326
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>

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stm32mp: add DT helper for reg by name

Add a new entry to find register properties by name and
include new assert functions to limit address cells to 1
and size cells to 1.

Change-Id: Ide59a795a05f

stm32mp: add DT helper for reg by name

Add a new entry to find register properties by name and
include new assert functions to limit address cells to 1
and size cells to 1.

Change-Id: Ide59a795a05fb2af36bd07fec15e5a3adf196226
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>

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stm32mp1: add compilation flags for boot devices

Adds compilation flags to specify which drivers will be
embedded in the generated firmware.

Change-Id: Ie9decc89c3f26cf17e7148a3a4cf337fd35940f7
Sig

stm32mp1: add compilation flags for boot devices

Adds compilation flags to specify which drivers will be
embedded in the generated firmware.

Change-Id: Ie9decc89c3f26cf17e7148a3a4cf337fd35940f7
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>

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Merge "zynqmp: pm: Add CLK_SET_RATE_PARENT in gem clock node" into integration

Merge changes from topic "add-versal-soc-support" into integration

* changes:
zynqmp: pm: clock: Move custom flags to typeflags
zynqmp: pm: clock: Add support for custom type flags
plat: xilin

Merge changes from topic "add-versal-soc-support" into integration

* changes:
zynqmp: pm: clock: Move custom flags to typeflags
zynqmp: pm: clock: Add support for custom type flags
plat: xilinx: zynqmp: Add GET_CALLBACK_DATA function
zynqmp: pm: Remove CLK_TOPSW_LSBUS from invalid clock list

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Tegra194: platform handler for entering CPU standby state

This patch implements a handler to enter the standby state on
Tegra194 platforms. On receiving a CPU_STANDBY state request,
the platform han

Tegra194: platform handler for entering CPU standby state

This patch implements a handler to enter the standby state on
Tegra194 platforms. On receiving a CPU_STANDBY state request,
the platform handler issues TEGRA_NVG_CORE_C6 request to the
MCE firmware to take the CPU into the standby state.

Change-Id: I703a96ec12205853ddb3c3871b23e338e1f60687
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra194: memctrl: force viw and vifalr/w transactions as non-coherent

Force memory transactions from viw and viflar/w as non-coherent from
no-override. This is necessary as iso clients shouldn't us

Tegra194: memctrl: force viw and vifalr/w transactions as non-coherent

Force memory transactions from viw and viflar/w as non-coherent from
no-override. This is necessary as iso clients shouldn't use coherent
path and stage-2 smmu mappings won't mark transactions as non-coherent.
For native case, no-override works. But, not for virtualization case.

Change-Id: I1a8fc17787c8d0f8579bdaeeb719084993e27276
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>

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Tegra194: memctrl: fix bug in client order id reg value generation

Client order id reset values are incorrectly and'ed with
mc_client_order_id macro, which resulted in getting reg value as
always ze

Tegra194: memctrl: fix bug in client order id reg value generation

Client order id reset values are incorrectly and'ed with
mc_client_order_id macro, which resulted in getting reg value as
always zero. Updated mc_client_order_id macro to avoid and'ing outside
the macro, to take the reg value and update specific bit field
as necessary.

Change-Id: I880be6e4291d7cd58cf70d7c247a4044e57edd9e
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>

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Tegra194: memctrl: enable mc coalescer

This patch enable the Memory Controller's "Coalescer" feature to
improve performance of memory transactions.

Change-Id: I50ba0354116284f85d9e170c293ce77e9f3fb

Tegra194: memctrl: enable mc coalescer

This patch enable the Memory Controller's "Coalescer" feature to
improve performance of memory transactions.

Change-Id: I50ba0354116284f85d9e170c293ce77e9f3fb4d8
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>

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Tegra194: update scratch registers used to read boot parameters

This patch changes SCRATCH_BOOT_PARAMS_ADDR macro to use SECURE_SCRATCH_RSV81
instead of SECURE_SCRATCH_RSV44. The previous level boot

Tegra194: update scratch registers used to read boot parameters

This patch changes SCRATCH_BOOT_PARAMS_ADDR macro to use SECURE_SCRATCH_RSV81
instead of SECURE_SCRATCH_RSV44. The previous level bootloader changed this
setting, so update here to keep both components in sync.

Change-Id: I4e0c1b54fc69482d5513a8608d0bf616677e1bdd
Signed-off-by: steven kao <skao@nvidia.com>

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Tegra194: implement system shutdown/reset handlers

This patch implements the PSCI system shutdown and reset handlers,
that in turn issue the MCE commands.

Change-Id: Ia9c831674d7be615a6e336abca42f3

Tegra194: implement system shutdown/reset handlers

This patch implements the PSCI system shutdown and reset handlers,
that in turn issue the MCE commands.

Change-Id: Ia9c831674d7be615a6e336abca42f397e4455572
Signed-off-by: Vignesh Radhakrishnan <vigneshr@nvidia.com>

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Tegra194: mce: support for shutdown and reboot

This patch adds support for shutdown/reboot handlers to the MCE
driver.

ATF communicates with mce using nvg interface for shutdown &
reboot. Both shut

Tegra194: mce: support for shutdown and reboot

This patch adds support for shutdown/reboot handlers to the MCE
driver.

ATF communicates with mce using nvg interface for shutdown &
reboot. Both shutdown and reboot use the same nvg index.
However, the 1st bit of the nvg data argument differentiates
whether its a shutdown or reboot.

Change-Id: Id2d1b0c4fec55abf69b7f8adb65ca70bfa920e73
Signed-off-by: Vignesh Radhakrishnan <vigneshr@nvidia.com>

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Tegra194: request CG7 before checking if SC7 is allowed

Currently firmware seems to be checking if we can get into system
suspend after checking if CC6 & C7 is allowed. For system suspend
to be trig

Tegra194: request CG7 before checking if SC7 is allowed

Currently firmware seems to be checking if we can get into system
suspend after checking if CC6 & C7 is allowed. For system suspend
to be triggered, the firmware needs to request for CG7 as well.

This patch fixes this anomaly.

Change-Id: I39c4c50092a4288f4f3fa4b0b1d5026be50f058f
Signed-off-by: Vignesh Radhakrishnan <vigneshr@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra194: config to enable/disable strict checking mode

This patch adds a new configuration option to the platform makefiles
that disables/enables strict checking mode. The config is enabled
by defa

Tegra194: config to enable/disable strict checking mode

This patch adds a new configuration option to the platform makefiles
that disables/enables strict checking mode. The config is enabled
by default.

Change-Id: I727dd0facee88d9517bf6956eaf9163eba25c8bb
Signed-off-by: Steven Kao <skao@nvidia.com>

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Tegra194: remove unused platform configs

This patch cleans the makefile to remove unused platform config
options.

Change-Id: I96d9795c0f0ba593de96017dc9a401d7c2ab471a
Signed-off-by: Varun Wadekar <

Tegra194: remove unused platform configs

This patch cleans the makefile to remove unused platform config
options.

Change-Id: I96d9795c0f0ba593de96017dc9a401d7c2ab471a
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra194: restore XUSB stream IDs on System Resume

The stream IDs for XUSB programmed during cold boot are lost on System
Suspend. This patch restores the XUSB stream IDs on System Resume.

NOTE: TH

Tegra194: restore XUSB stream IDs on System Resume

The stream IDs for XUSB programmed during cold boot are lost on System
Suspend. This patch restores the XUSB stream IDs on System Resume.

NOTE: THE WARMBOOT CODE NEEDS TO MAKE SURE THAT THE XUSB MODULE IS OUT
OF RESET AND THE CLOCKS ARE ENABLED, BEFORE POWERING ON THE CPU, DURING
SYSTEM RESUME.

Change-Id: Ibd5f1e5ebacffa6b29b625f4c41ecf204afa8191
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Merge "rcar_gen3: Add missing #{address,size}-cells into generated DT" into integration

intel: Add function to check fpga readiness

Create a function to check for fpga readiness, and move the checking out
of bridge enable function.

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.ab

intel: Add function to check fpga readiness

Create a function to check for fpga readiness, and move the checking out
of bridge enable function.

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I3f473ffeffa9ce181a48977560c8bda19c6123c0

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intel: Add bridge control for FPGA reconfig

This is to make sure that bridge access in disabled before doing full
FPGA reconfiguration and turn re-enable it once the configuration
succeed.

Signed-o

intel: Add bridge control for FPGA reconfig

This is to make sure that bridge access in disabled before doing full
FPGA reconfiguration and turn re-enable it once the configuration
succeed.

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I1f42fbf04ac1625048bbdf21b8a0443464ed833d

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intel: FPGA config_isdone() status query

SiP CONFIG_ISDONE now will query status for either CONFIG_STATUS or
RECONFIG_STATUS based on passed parameter

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asy

intel: FPGA config_isdone() status query

SiP CONFIG_ISDONE now will query status for either CONFIG_STATUS or
RECONFIG_STATUS based on passed parameter

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Idb8a84af4e98654759843de09a289d31246c9a91

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