1Build Options 2============= 3 4The TF-A build system supports the following build options. Unless mentioned 5otherwise, these options are expected to be specified at the build command 6line and are not to be modified in any component makefiles. Note that the 7build system doesn't track dependency for build options. Therefore, if any of 8the build options are changed from a previous build, a clean build must be 9performed. 10 11.. _build_options_common: 12 13Common build options 14-------------------- 15 16- ``AARCH32_INSTRUCTION_SET``: Choose the AArch32 instruction set that the 17 compiler should use. Valid values are T32 and A32. It defaults to T32 due to 18 code having a smaller resulting size. 19 20- ``AARCH32_SP`` : Choose the AArch32 Secure Payload component to be built as 21 as the BL32 image when ``ARCH=aarch32``. The value should be the path to the 22 directory containing the SP source, relative to the ``bl32/``; the directory 23 is expected to contain a makefile called ``<aarch32_sp-value>.mk``. 24 25- ``ARCH`` : Choose the target build architecture for TF-A. It can take either 26 ``aarch64`` or ``aarch32`` as values. By default, it is defined to 27 ``aarch64``. 28 29- ``ARM_ARCH_MAJOR``: The major version of Arm Architecture to target when 30 compiling TF-A. Its value must be numeric, and defaults to 8 . See also, 31 *Armv8 Architecture Extensions* and *Armv7 Architecture Extensions* in 32 :ref:`Firmware Design`. 33 34- ``ARM_ARCH_MINOR``: The minor version of Arm Architecture to target when 35 compiling TF-A. Its value must be a numeric, and defaults to 0. See also, 36 *Armv8 Architecture Extensions* in :ref:`Firmware Design`. 37 38- ``BL2``: This is an optional build option which specifies the path to BL2 39 image for the ``fip`` target. In this case, the BL2 in the TF-A will not be 40 built. 41 42- ``BL2U``: This is an optional build option which specifies the path to 43 BL2U image. In this case, the BL2U in TF-A will not be built. 44 45- ``BL2_AT_EL3``: This is an optional build option that enables the use of 46 BL2 at EL3 execution level. 47 48- ``BL2_IN_XIP_MEM``: In some use-cases BL2 will be stored in eXecute In Place 49 (XIP) memory, like BL1. In these use-cases, it is necessary to initialize 50 the RW sections in RAM, while leaving the RO sections in place. This option 51 enable this use-case. For now, this option is only supported when BL2_AT_EL3 52 is set to '1'. 53 54- ``BL31``: This is an optional build option which specifies the path to 55 BL31 image for the ``fip`` target. In this case, the BL31 in TF-A will not 56 be built. 57 58- ``BL31_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the 59 file that contains the BL31 private key in PEM format. If ``SAVE_KEYS=1``, 60 this file name will be used to save the key. 61 62- ``BL32``: This is an optional build option which specifies the path to 63 BL32 image for the ``fip`` target. In this case, the BL32 in TF-A will not 64 be built. 65 66- ``BL32_EXTRA1``: This is an optional build option which specifies the path to 67 Trusted OS Extra1 image for the ``fip`` target. 68 69- ``BL32_EXTRA2``: This is an optional build option which specifies the path to 70 Trusted OS Extra2 image for the ``fip`` target. 71 72- ``BL32_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the 73 file that contains the BL32 private key in PEM format. If ``SAVE_KEYS=1``, 74 this file name will be used to save the key. 75 76- ``BL33``: Path to BL33 image in the host file system. This is mandatory for 77 ``fip`` target in case TF-A BL2 is used. 78 79- ``BL33_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the 80 file that contains the BL33 private key in PEM format. If ``SAVE_KEYS=1``, 81 this file name will be used to save the key. 82 83- ``BRANCH_PROTECTION``: Numeric value to enable ARMv8.3 Pointer Authentication 84 and ARMv8.5 Branch Target Identification support for TF-A BL images themselves. 85 If enabled, it is needed to use a compiler that supports the option 86 ``-mbranch-protection``. Selects the branch protection features to use: 87- 0: Default value turns off all types of branch protection 88- 1: Enables all types of branch protection features 89- 2: Return address signing to its standard level 90- 3: Extend the signing to include leaf functions 91 92 The table below summarizes ``BRANCH_PROTECTION`` values, GCC compilation options 93 and resulting PAuth/BTI features. 94 95 +-------+--------------+-------+-----+ 96 | Value | GCC option | PAuth | BTI | 97 +=======+==============+=======+=====+ 98 | 0 | none | N | N | 99 +-------+--------------+-------+-----+ 100 | 1 | standard | Y | Y | 101 +-------+--------------+-------+-----+ 102 | 2 | pac-ret | Y | N | 103 +-------+--------------+-------+-----+ 104 | 3 | pac-ret+leaf | Y | N | 105 +-------+--------------+-------+-----+ 106 107 This option defaults to 0 and this is an experimental feature. 108 Note that Pointer Authentication is enabled for Non-secure world 109 irrespective of the value of this option if the CPU supports it. 110 111- ``BUILD_MESSAGE_TIMESTAMP``: String used to identify the time and date of the 112 compilation of each build. It must be set to a C string (including quotes 113 where applicable). Defaults to a string that contains the time and date of 114 the compilation. 115 116- ``BUILD_STRING``: Input string for VERSION_STRING, which allows the TF-A 117 build to be uniquely identified. Defaults to the current git commit id. 118 119- ``CFLAGS``: Extra user options appended on the compiler's command line in 120 addition to the options set by the build system. 121 122- ``COLD_BOOT_SINGLE_CPU``: This option indicates whether the platform may 123 release several CPUs out of reset. It can take either 0 (several CPUs may be 124 brought up) or 1 (only one CPU will ever be brought up during cold reset). 125 Default is 0. If the platform always brings up a single CPU, there is no 126 need to distinguish between primary and secondary CPUs and the boot path can 127 be optimised. The ``plat_is_my_cpu_primary()`` and 128 ``plat_secondary_cold_boot_setup()`` platform porting interfaces do not need 129 to be implemented in this case. 130 131- ``COT``: When Trusted Boot is enabled, selects the desired chain of trust. 132 Defaults to ``tbbr``. 133 134- ``CRASH_REPORTING``: A non-zero value enables a console dump of processor 135 register state when an unexpected exception occurs during execution of 136 BL31. This option defaults to the value of ``DEBUG`` - i.e. by default 137 this is only enabled for a debug build of the firmware. 138 139- ``CREATE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the 140 certificate generation tool to create new keys in case no valid keys are 141 present or specified. Allowed options are '0' or '1'. Default is '1'. 142 143- ``CTX_INCLUDE_AARCH32_REGS`` : Boolean option that, when set to 1, will cause 144 the AArch32 system registers to be included when saving and restoring the 145 CPU context. The option must be set to 0 for AArch64-only platforms (that 146 is on hardware that does not implement AArch32, or at least not at EL1 and 147 higher ELs). Default value is 1. 148 149- ``CTX_INCLUDE_FPREGS``: Boolean option that, when set to 1, will cause the FP 150 registers to be included when saving and restoring the CPU context. Default 151 is 0. 152 153- ``CTX_INCLUDE_PAUTH_REGS``: Boolean option that, when set to 1, enables 154 Pointer Authentication for Secure world. This will cause the ARMv8.3-PAuth 155 registers to be included when saving and restoring the CPU context as 156 part of world switch. Default value is 0 and this is an experimental feature. 157 Note that Pointer Authentication is enabled for Non-secure world irrespective 158 of the value of this flag if the CPU supports it. 159 160- ``DEBUG``: Chooses between a debug and release build. It can take either 0 161 (release) or 1 (debug) as values. 0 is the default. 162 163- ``DISABLE_BIN_GENERATION``: Boolean option to disable the generation 164 of the binary image. If set to 1, then only the ELF image is built. 165 0 is the default. 166 167- ``DYN_DISABLE_AUTH``: Provides the capability to dynamically disable Trusted 168 Board Boot authentication at runtime. This option is meant to be enabled only 169 for development platforms. ``TRUSTED_BOARD_BOOT`` flag must be set if this 170 flag has to be enabled. 0 is the default. 171 172- ``E``: Boolean option to make warnings into errors. Default is 1. 173 174- ``EL3_PAYLOAD_BASE``: This option enables booting an EL3 payload instead of 175 the normal boot flow. It must specify the entry point address of the EL3 176 payload. Please refer to the "Booting an EL3 payload" section for more 177 details. 178 179- ``ENABLE_AMU``: Boolean option to enable Activity Monitor Unit extensions. 180 This is an optional architectural feature available on v8.4 onwards. Some 181 v8.2 implementations also implement an AMU and this option can be used to 182 enable this feature on those systems as well. Default is 0. 183 184- ``ENABLE_ASSERTIONS``: This option controls whether or not calls to ``assert()`` 185 are compiled out. For debug builds, this option defaults to 1, and calls to 186 ``assert()`` are left in place. For release builds, this option defaults to 0 187 and calls to ``assert()`` function are compiled out. This option can be set 188 independently of ``DEBUG``. It can also be used to hide any auxiliary code 189 that is only required for the assertion and does not fit in the assertion 190 itself. 191 192- ``ENABLE_BACKTRACE``: This option controls whether to enables backtrace 193 dumps or not. It is supported in both AArch64 and AArch32. However, in 194 AArch32 the format of the frame records are not defined in the AAPCS and they 195 are defined by the implementation. This implementation of backtrace only 196 supports the format used by GCC when T32 interworking is disabled. For this 197 reason enabling this option in AArch32 will force the compiler to only 198 generate A32 code. This option is enabled by default only in AArch64 debug 199 builds, but this behaviour can be overridden in each platform's Makefile or 200 in the build command line. 201 202- ``ENABLE_LTO``: Boolean option to enable Link Time Optimization (LTO) 203 support in GCC for TF-A. This option is currently only supported for 204 AArch64. Default is 0. 205 206- ``ENABLE_MPAM_FOR_LOWER_ELS``: Boolean option to enable lower ELs to use MPAM 207 feature. MPAM is an optional Armv8.4 extension that enables various memory 208 system components and resources to define partitions; software running at 209 various ELs can assign themselves to desired partition to control their 210 performance aspects. 211 212 When this option is set to ``1``, EL3 allows lower ELs to access their own 213 MPAM registers without trapping into EL3. This option doesn't make use of 214 partitioning in EL3, however. Platform initialisation code should configure 215 and use partitions in EL3 as required. This option defaults to ``0``. 216 217- ``ENABLE_PIE``: Boolean option to enable Position Independent Executable(PIE) 218 support within generic code in TF-A. This option is currently only supported 219 in BL2_AT_EL3, BL31, and BL32 (TSP). Default is 0. 220 221- ``ENABLE_PMF``: Boolean option to enable support for optional Performance 222 Measurement Framework(PMF). Default is 0. 223 224- ``ENABLE_PSCI_STAT``: Boolean option to enable support for optional PSCI 225 functions ``PSCI_STAT_RESIDENCY`` and ``PSCI_STAT_COUNT``. Default is 0. 226 In the absence of an alternate stat collection backend, ``ENABLE_PMF`` must 227 be enabled. If ``ENABLE_PMF`` is set, the residency statistics are tracked in 228 software. 229 230- ``ENABLE_RUNTIME_INSTRUMENTATION``: Boolean option to enable runtime 231 instrumentation which injects timestamp collection points into TF-A to 232 allow runtime performance to be measured. Currently, only PSCI is 233 instrumented. Enabling this option enables the ``ENABLE_PMF`` build option 234 as well. Default is 0. 235 236- ``ENABLE_SPE_FOR_LOWER_ELS`` : Boolean option to enable Statistical Profiling 237 extensions. This is an optional architectural feature for AArch64. 238 The default is 1 but is automatically disabled when the target architecture 239 is AArch32. 240 241- ``ENABLE_SVE_FOR_NS``: Boolean option to enable Scalable Vector Extension 242 (SVE) for the Non-secure world only. SVE is an optional architectural feature 243 for AArch64. Note that when SVE is enabled for the Non-secure world, access 244 to SIMD and floating-point functionality from the Secure world is disabled. 245 This is to avoid corruption of the Non-secure world data in the Z-registers 246 which are aliased by the SIMD and FP registers. The build option is not 247 compatible with the ``CTX_INCLUDE_FPREGS`` build option, and will raise an 248 assert on platforms where SVE is implemented and ``ENABLE_SVE_FOR_NS`` set to 249 1. The default is 1 but is automatically disabled when the target 250 architecture is AArch32. 251 252- ``ENABLE_STACK_PROTECTOR``: String option to enable the stack protection 253 checks in GCC. Allowed values are "all", "strong", "default" and "none". The 254 default value is set to "none". "strong" is the recommended stack protection 255 level if this feature is desired. "none" disables the stack protection. For 256 all values other than "none", the ``plat_get_stack_protector_canary()`` 257 platform hook needs to be implemented. The value is passed as the last 258 component of the option ``-fstack-protector-$ENABLE_STACK_PROTECTOR``. 259 260- ``ERROR_DEPRECATED``: This option decides whether to treat the usage of 261 deprecated platform APIs, helper functions or drivers within Trusted 262 Firmware as error. It can take the value 1 (flag the use of deprecated 263 APIs as error) or 0. The default is 0. 264 265- ``EL3_EXCEPTION_HANDLING``: When set to ``1``, enable handling of exceptions 266 targeted at EL3. When set ``0`` (default), no exceptions are expected or 267 handled at EL3, and a panic will result. This is supported only for AArch64 268 builds. 269 270- ``FAULT_INJECTION_SUPPORT``: ARMv8.4 extensions introduced support for fault 271 injection from lower ELs, and this build option enables lower ELs to use 272 Error Records accessed via System Registers to inject faults. This is 273 applicable only to AArch64 builds. 274 275 This feature is intended for testing purposes only, and is advisable to keep 276 disabled for production images. 277 278- ``FIP_NAME``: This is an optional build option which specifies the FIP 279 filename for the ``fip`` target. Default is ``fip.bin``. 280 281- ``FWU_FIP_NAME``: This is an optional build option which specifies the FWU 282 FIP filename for the ``fwu_fip`` target. Default is ``fwu_fip.bin``. 283 284- ``GENERATE_COT``: Boolean flag used to build and execute the ``cert_create`` 285 tool to create certificates as per the Chain of Trust described in 286 :ref:`Trusted Board Boot`. The build system then calls ``fiptool`` to 287 include the certificates in the FIP and FWU_FIP. Default value is '0'. 288 289 Specify both ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=1`` to include support 290 for the Trusted Board Boot feature in the BL1 and BL2 images, to generate 291 the corresponding certificates, and to include those certificates in the 292 FIP and FWU_FIP. 293 294 Note that if ``TRUSTED_BOARD_BOOT=0`` and ``GENERATE_COT=1``, the BL1 and BL2 295 images will not include support for Trusted Board Boot. The FIP will still 296 include the corresponding certificates. This FIP can be used to verify the 297 Chain of Trust on the host machine through other mechanisms. 298 299 Note that if ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=0``, the BL1 and BL2 300 images will include support for Trusted Board Boot, but the FIP and FWU_FIP 301 will not include the corresponding certificates, causing a boot failure. 302 303- ``GICV2_G0_FOR_EL3``: Unlike GICv3, the GICv2 architecture doesn't have 304 inherent support for specific EL3 type interrupts. Setting this build option 305 to ``1`` assumes GICv2 *Group 0* interrupts are expected to target EL3, both 306 by `platform abstraction layer`__ and `Interrupt Management Framework`__. 307 This allows GICv2 platforms to enable features requiring EL3 interrupt type. 308 This also means that all GICv2 Group 0 interrupts are delivered to EL3, and 309 the Secure Payload interrupts needs to be synchronously handed over to Secure 310 EL1 for handling. The default value of this option is ``0``, which means the 311 Group 0 interrupts are assumed to be handled by Secure EL1. 312 313 .. __: `platform-interrupt-controller-API.rst` 314 .. __: `interrupt-framework-design.rst` 315 316- ``HANDLE_EA_EL3_FIRST``: When set to ``1``, External Aborts and SError 317 Interrupts will be always trapped in EL3 i.e. in BL31 at runtime. When set to 318 ``0`` (default), these exceptions will be trapped in the current exception 319 level (or in EL1 if the current exception level is EL0). 320 321- ``HW_ASSISTED_COHERENCY``: On most Arm systems to-date, platform-specific 322 software operations are required for CPUs to enter and exit coherency. 323 However, newer systems exist where CPUs' entry to and exit from coherency 324 is managed in hardware. Such systems require software to only initiate these 325 operations, and the rest is managed in hardware, minimizing active software 326 management. In such systems, this boolean option enables TF-A to carry out 327 build and run-time optimizations during boot and power management operations. 328 This option defaults to 0 and if it is enabled, then it implies 329 ``WARMBOOT_ENABLE_DCACHE_EARLY`` is also enabled. 330 331 If this flag is disabled while the platform which TF-A is compiled for 332 includes cores that manage coherency in hardware, then a compilation error is 333 generated. This is based on the fact that a system cannot have, at the same 334 time, cores that manage coherency in hardware and cores that don't. In other 335 words, a platform cannot have, at the same time, cores that require 336 ``HW_ASSISTED_COHERENCY=1`` and cores that require 337 ``HW_ASSISTED_COHERENCY=0``. 338 339 Note that, when ``HW_ASSISTED_COHERENCY`` is enabled, version 2 of 340 translation library (xlat tables v2) must be used; version 1 of translation 341 library is not supported. 342 343- ``JUNO_AARCH32_EL3_RUNTIME``: This build flag enables you to execute EL3 344 runtime software in AArch32 mode, which is required to run AArch32 on Juno. 345 By default this flag is set to '0'. Enabling this flag builds BL1 and BL2 in 346 AArch64 and facilitates the loading of ``SP_MIN`` and BL33 as AArch32 executable 347 images. 348 349- ``KEY_ALG``: This build flag enables the user to select the algorithm to be 350 used for generating the PKCS keys and subsequent signing of the certificate. 351 It accepts 3 values: ``rsa``, ``rsa_1_5`` and ``ecdsa``. The option 352 ``rsa_1_5`` is the legacy PKCS#1 RSA 1.5 algorithm which is not TBBR 353 compliant and is retained only for compatibility. The default value of this 354 flag is ``rsa`` which is the TBBR compliant PKCS#1 RSA 2.1 scheme. 355 356- ``KEY_SIZE``: This build flag enables the user to select the key size for 357 the algorithm specified by ``KEY_ALG``. The valid values for ``KEY_SIZE`` 358 depend on the chosen algorithm and the cryptographic module. 359 360 +-----------+------------------------------------+ 361 | KEY_ALG | Possible key sizes | 362 +===========+====================================+ 363 | rsa | 1024 , 2048 (default), 3072, 4096* | 364 +-----------+------------------------------------+ 365 | ecdsa | unavailable | 366 +-----------+------------------------------------+ 367 368 * Only 2048 bits size is available with CryptoCell 712 SBROM release 1. 369 Only 3072 bits size is available with CryptoCell 712 SBROM release 2. 370 371- ``HASH_ALG``: This build flag enables the user to select the secure hash 372 algorithm. It accepts 3 values: ``sha256``, ``sha384`` and ``sha512``. 373 The default value of this flag is ``sha256``. 374 375- ``LDFLAGS``: Extra user options appended to the linkers' command line in 376 addition to the one set by the build system. 377 378- ``LOG_LEVEL``: Chooses the log level, which controls the amount of console log 379 output compiled into the build. This should be one of the following: 380 381 :: 382 383 0 (LOG_LEVEL_NONE) 384 10 (LOG_LEVEL_ERROR) 385 20 (LOG_LEVEL_NOTICE) 386 30 (LOG_LEVEL_WARNING) 387 40 (LOG_LEVEL_INFO) 388 50 (LOG_LEVEL_VERBOSE) 389 390 All log output up to and including the selected log level is compiled into 391 the build. The default value is 40 in debug builds and 20 in release builds. 392 393- ``NON_TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It 394 specifies the file that contains the Non-Trusted World private key in PEM 395 format. If ``SAVE_KEYS=1``, this file name will be used to save the key. 396 397- ``NS_BL2U``: Path to NS_BL2U image in the host file system. This image is 398 optional. It is only needed if the platform makefile specifies that it 399 is required in order to build the ``fwu_fip`` target. 400 401- ``NS_TIMER_SWITCH``: Enable save and restore for non-secure timer register 402 contents upon world switch. It can take either 0 (don't save and restore) or 403 1 (do save and restore). 0 is the default. An SPD may set this to 1 if it 404 wants the timer registers to be saved and restored. 405 406- ``OVERRIDE_LIBC``: This option allows platforms to override the default libc 407 for the BL image. It can be either 0 (include) or 1 (remove). The default 408 value is 0. 409 410- ``PL011_GENERIC_UART``: Boolean option to indicate the PL011 driver that 411 the underlying hardware is not a full PL011 UART but a minimally compliant 412 generic UART, which is a subset of the PL011. The driver will not access 413 any register that is not part of the SBSA generic UART specification. 414 Default value is 0 (a full PL011 compliant UART is present). 415 416- ``PLAT``: Choose a platform to build TF-A for. The chosen platform name 417 must be subdirectory of any depth under ``plat/``, and must contain a 418 platform makefile named ``platform.mk``. For example, to build TF-A for the 419 Arm Juno board, select PLAT=juno. 420 421- ``PRELOADED_BL33_BASE``: This option enables booting a preloaded BL33 image 422 instead of the normal boot flow. When defined, it must specify the entry 423 point address for the preloaded BL33 image. This option is incompatible with 424 ``EL3_PAYLOAD_BASE``. If both are defined, ``EL3_PAYLOAD_BASE`` has priority 425 over ``PRELOADED_BL33_BASE``. 426 427- ``PROGRAMMABLE_RESET_ADDRESS``: This option indicates whether the reset 428 vector address can be programmed or is fixed on the platform. It can take 429 either 0 (fixed) or 1 (programmable). Default is 0. If the platform has a 430 programmable reset address, it is expected that a CPU will start executing 431 code directly at the right address, both on a cold and warm reset. In this 432 case, there is no need to identify the entrypoint on boot and the boot path 433 can be optimised. The ``plat_get_my_entrypoint()`` platform porting interface 434 does not need to be implemented in this case. 435 436- ``PSCI_EXTENDED_STATE_ID``: As per PSCI1.0 Specification, there are 2 formats 437 possible for the PSCI power-state parameter: original and extended State-ID 438 formats. This flag if set to 1, configures the generic PSCI layer to use the 439 extended format. The default value of this flag is 0, which means by default 440 the original power-state format is used by the PSCI implementation. This flag 441 should be specified by the platform makefile and it governs the return value 442 of PSCI_FEATURES API for CPU_SUSPEND smc function id. When this option is 443 enabled on Arm platforms, the option ``ARM_RECOM_STATE_ID_ENC`` needs to be 444 set to 1 as well. 445 446- ``RAS_EXTENSION``: When set to ``1``, enable Armv8.2 RAS features. RAS features 447 are an optional extension for pre-Armv8.2 CPUs, but are mandatory for Armv8.2 448 or later CPUs. 449 450 When ``RAS_EXTENSION`` is set to ``1``, ``HANDLE_EA_EL3_FIRST`` must also be 451 set to ``1``. 452 453 This option is disabled by default. 454 455- ``RESET_TO_BL31``: Enable BL31 entrypoint as the CPU reset vector instead 456 of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 457 entrypoint) or 1 (CPU reset to BL31 entrypoint). 458 The default value is 0. 459 460- ``RESET_TO_SP_MIN``: SP_MIN is the minimal AArch32 Secure Payload provided 461 in TF-A. This flag configures SP_MIN entrypoint as the CPU reset vector 462 instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 463 entrypoint) or 1 (CPU reset to SP_MIN entrypoint). The default value is 0. 464 465- ``ROT_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the 466 file that contains the ROT private key in PEM format. If ``SAVE_KEYS=1``, this 467 file name will be used to save the key. 468 469- ``SAVE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the 470 certificate generation tool to save the keys used to establish the Chain of 471 Trust. Allowed options are '0' or '1'. Default is '0' (do not save). 472 473- ``SCP_BL2``: Path to SCP_BL2 image in the host file system. This image is optional. 474 If a SCP_BL2 image is present then this option must be passed for the ``fip`` 475 target. 476 477- ``SCP_BL2_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the 478 file that contains the SCP_BL2 private key in PEM format. If ``SAVE_KEYS=1``, 479 this file name will be used to save the key. 480 481- ``SCP_BL2U``: Path to SCP_BL2U image in the host file system. This image is 482 optional. It is only needed if the platform makefile specifies that it 483 is required in order to build the ``fwu_fip`` target. 484 485- ``SDEI_SUPPORT``: Setting this to ``1`` enables support for Software 486 Delegated Exception Interface to BL31 image. This defaults to ``0``. 487 488 When set to ``1``, the build option ``EL3_EXCEPTION_HANDLING`` must also be 489 set to ``1``. 490 491- ``SEPARATE_CODE_AND_RODATA``: Whether code and read-only data should be 492 isolated on separate memory pages. This is a trade-off between security and 493 memory usage. See "Isolating code and read-only data on separate memory 494 pages" section in :ref:`Firmware Design`. This flag is disabled by default and 495 affects all BL images. 496 497- ``SEPARATE_NOBITS_REGION``: Setting this option to ``1`` allows the NOBITS 498 sections of BL31 (.bss, stacks, page tables, and coherent memory) to be 499 allocated in RAM discontiguous from the loaded firmware image. When set, the 500 platform is expected to provide definitons for ``BL31_NOBITS_BASE`` and 501 ``BL31_NOBITS_LIMIT``. When the option is ``0`` (the default), NOBITS 502 sections are placed in RAM immediately following the loaded firmware image. 503 504- ``SPD``: Choose a Secure Payload Dispatcher component to be built into TF-A. 505 This build option is only valid if ``ARCH=aarch64``. The value should be 506 the path to the directory containing the SPD source, relative to 507 ``services/spd/``; the directory is expected to contain a makefile called 508 ``<spd-value>.mk``. 509 510- ``SPIN_ON_BL1_EXIT``: This option introduces an infinite loop in BL1. It can 511 take either 0 (no loop) or 1 (add a loop). 0 is the default. This loop stops 512 execution in BL1 just before handing over to BL31. At this point, all 513 firmware images have been loaded in memory, and the MMU and caches are 514 turned off. Refer to the "Debugging options" section for more details. 515 516- ``SPM_MM`` : Boolean option to enable the Management Mode (MM)-based Secure 517 Partition Manager (SPM) implementation. The default value is ``0``. 518 519- ``SP_MIN_WITH_SECURE_FIQ``: Boolean flag to indicate the SP_MIN handles 520 secure interrupts (caught through the FIQ line). Platforms can enable 521 this directive if they need to handle such interruption. When enabled, 522 the FIQ are handled in monitor mode and non secure world is not allowed 523 to mask these events. Platforms that enable FIQ handling in SP_MIN shall 524 implement the api ``sp_min_plat_fiq_handler()``. The default value is 0. 525 526- ``TRUSTED_BOARD_BOOT``: Boolean flag to include support for the Trusted Board 527 Boot feature. When set to '1', BL1 and BL2 images include support to load 528 and verify the certificates and images in a FIP, and BL1 includes support 529 for the Firmware Update. The default value is '0'. Generation and inclusion 530 of certificates in the FIP and FWU_FIP depends upon the value of the 531 ``GENERATE_COT`` option. 532 533 .. warning:: 534 This option depends on ``CREATE_KEYS`` to be enabled. If the keys 535 already exist in disk, they will be overwritten without further notice. 536 537- ``TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It 538 specifies the file that contains the Trusted World private key in PEM 539 format. If ``SAVE_KEYS=1``, this file name will be used to save the key. 540 541- ``TSP_INIT_ASYNC``: Choose BL32 initialization method as asynchronous or 542 synchronous, (see "Initializing a BL32 Image" section in 543 :ref:`Firmware Design`). It can take the value 0 (BL32 is initialized using 544 synchronous method) or 1 (BL32 is initialized using asynchronous method). 545 Default is 0. 546 547- ``TSP_NS_INTR_ASYNC_PREEMPT``: A non zero value enables the interrupt 548 routing model which routes non-secure interrupts asynchronously from TSP 549 to EL3 causing immediate preemption of TSP. The EL3 is responsible 550 for saving and restoring the TSP context in this routing model. The 551 default routing model (when the value is 0) is to route non-secure 552 interrupts to TSP allowing it to save its context and hand over 553 synchronously to EL3 via an SMC. 554 555 .. note:: 556 When ``EL3_EXCEPTION_HANDLING`` is ``1``, ``TSP_NS_INTR_ASYNC_PREEMPT`` 557 must also be set to ``1``. 558 559- ``USE_ARM_LINK``: This flag determines whether to enable support for ARM 560 linker. When the ``LINKER`` build variable points to the armlink linker, 561 this flag is enabled automatically. To enable support for armlink, platforms 562 will have to provide a scatter file for the BL image. Currently, Tegra 563 platforms use the armlink support to compile BL3-1 images. 564 565- ``USE_COHERENT_MEM``: This flag determines whether to include the coherent 566 memory region in the BL memory map or not (see "Use of Coherent memory in 567 TF-A" section in :ref:`Firmware Design`). It can take the value 1 568 (Coherent memory region is included) or 0 (Coherent memory region is 569 excluded). Default is 1. 570 571- ``USE_DEBUGFS``: When set to 1 this option activates an EXPERIMENTAL feature 572 exposing a virtual filesystem interface through BL31 as a SiP SMC function. 573 Default is 0. 574 575- ``USE_ROMLIB``: This flag determines whether library at ROM will be used. 576 This feature creates a library of functions to be placed in ROM and thus 577 reduces SRAM usage. Refer to :ref:`Library at ROM` for further details. Default 578 is 0. 579 580- ``V``: Verbose build. If assigned anything other than 0, the build commands 581 are printed. Default is 0. 582 583- ``VERSION_STRING``: String used in the log output for each TF-A image. 584 Defaults to a string formed by concatenating the version number, build type 585 and build string. 586 587- ``W``: Warning level. Some compiler warning options of interest have been 588 regrouped and put in the root Makefile. This flag can take the values 0 to 3, 589 each level enabling more warning options. Default is 0. 590 591- ``WARMBOOT_ENABLE_DCACHE_EARLY`` : Boolean option to enable D-cache early on 592 the CPU after warm boot. This is applicable for platforms which do not 593 require interconnect programming to enable cache coherency (eg: single 594 cluster platforms). If this option is enabled, then warm boot path 595 enables D-caches immediately after enabling MMU. This option defaults to 0. 596 597Debugging options 598----------------- 599 600To compile a debug version and make the build more verbose use 601 602.. code:: shell 603 604 make PLAT=<platform> DEBUG=1 V=1 all 605 606AArch64 GCC uses DWARF version 4 debugging symbols by default. Some tools (for 607example DS-5) might not support this and may need an older version of DWARF 608symbols to be emitted by GCC. This can be achieved by using the 609``-gdwarf-<version>`` flag, with the version being set to 2 or 3. Setting the 610version to 2 is recommended for DS-5 versions older than 5.16. 611 612When debugging logic problems it might also be useful to disable all compiler 613optimizations by using ``-O0``. 614 615.. warning:: 616 Using ``-O0`` could cause output images to be larger and base addresses 617 might need to be recalculated (see the **Memory layout on Arm development 618 platforms** section in the :ref:`Firmware Design`). 619 620Extra debug options can be passed to the build system by setting ``CFLAGS`` or 621``LDFLAGS``: 622 623.. code:: shell 624 625 CFLAGS='-O0 -gdwarf-2' \ 626 make PLAT=<platform> DEBUG=1 V=1 all 627 628Note that using ``-Wl,`` style compilation driver options in ``CFLAGS`` will be 629ignored as the linker is called directly. 630 631It is also possible to introduce an infinite loop to help in debugging the 632post-BL2 phase of TF-A. This can be done by rebuilding BL1 with the 633``SPIN_ON_BL1_EXIT=1`` build flag. Refer to the :ref:`build_options_common` 634section. In this case, the developer may take control of the target using a 635debugger when indicated by the console output. When using DS-5, the following 636commands can be used: 637 638:: 639 640 # Stop target execution 641 interrupt 642 643 # 644 # Prepare your debugging environment, e.g. set breakpoints 645 # 646 647 # Jump over the debug loop 648 set var $AARCH64::$Core::$PC = $AARCH64::$Core::$PC + 4 649 650 # Resume execution 651 continue 652 653-------------- 654 655*Copyright (c) 2019, Arm Limited. All rights reserved.* 656