uniphier: make I/O register region configurable

The I/O register region will be changed in the next SoC. Make it
configurable.

Change-Id: Iec0cbd1ef2d0703ebc7c3d3082edd73791bbfec9
Signed-off-by: Ma

uniphier: make I/O register region configurable

The I/O register region will be changed in the next SoC. Make it
configurable.

Change-Id: Iec0cbd1ef2d0703ebc7c3d3082edd73791bbfec9
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

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uniphier: extend boot device detection for future SoCs

The next SoC will have:
- No boot swap
- SD boot
- No USB boot

Add new fields to handle this.

Change-Id: I772395f2c5dfc612e575b0cbd0657

uniphier: extend boot device detection for future SoCs

The next SoC will have:
- No boot swap
- SD boot
- No USB boot

Add new fields to handle this.

Change-Id: I772395f2c5dfc612e575b0cbd0657a5fa9611c25
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

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uniphier: make PSCI related base address configurable

The register base address will be changed in the next SoC. Make it
configurable.

Change-Id: Ibe07bd9db128b0f7e629916cb6ae21ba7984eca9
Signed-of

uniphier: make PSCI related base address configurable

The register base address will be changed in the next SoC. Make it
configurable.

Change-Id: Ibe07bd9db128b0f7e629916cb6ae21ba7984eca9
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

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uniphier: change block_addressing flag to bool

The flag, uniphier_emmc_block_addressing, is boolean logic, so
"bool' is more suitable.

uniphier_emmc_is_over_2gb() is not boolean - it returns 1 / 0

uniphier: change block_addressing flag to bool

The flag, uniphier_emmc_block_addressing, is boolean logic, so
"bool' is more suitable.

uniphier_emmc_is_over_2gb() is not boolean - it returns 1 / 0
depending on the card density, or a negative value on failure.
Rename it to make it less confusing.

Change-Id: Ia646b1929147b644e0df07c46b54ab80548bc3bd
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

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uniphier: make counter control base address configurable

The register base will be changed in the next SoC. Make it
configurable.

Change-Id: I4a7cf85fe50e4d71db58a3372a71774e43193bd3
Signed-off-by:

uniphier: make counter control base address configurable

The register base will be changed in the next SoC. Make it
configurable.

Change-Id: I4a7cf85fe50e4d71db58a3372a71774e43193bd3
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

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uniphier: change the return value type of .is_usb_boot() to bool

This is boolean logic, so "bool" is more suitable.

Change-Id: I439c5099770600a65b8f58390a4c621c2ee487a5
Signed-off-by: Masahiro Yama

uniphier: change the return value type of .is_usb_boot() to bool

This is boolean logic, so "bool" is more suitable.

Change-Id: I439c5099770600a65b8f58390a4c621c2ee487a5
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

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uniphier: make UART base address configurable

The next SoC supports the same UART, but the register base will be
changed. Make it configurable.

Change-Id: Ida5c9151b2f3554afd15555b22838437eef443f7

uniphier: make UART base address configurable

The next SoC supports the same UART, but the register base will be
changed. Make it configurable.

Change-Id: Ida5c9151b2f3554afd15555b22838437eef443f7
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

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uniphier: make pinmon base address configurable

The register base will be changed in the next SoC. Make it
configurable.

Change-Id: I9fbb6bdd1cf06207618742d4ad7970d911c9bc26
Signed-off-by: Masahiro

uniphier: make pinmon base address configurable

The register base will be changed in the next SoC. Make it
configurable.

Change-Id: I9fbb6bdd1cf06207618742d4ad7970d911c9bc26
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

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uniphier: make NAND controller base address configurable

The next SoC does not support the NAND controller, but make the base
address configurable for consistency and future proof.

Change-Id: I776e

uniphier: make NAND controller base address configurable

The next SoC does not support the NAND controller, but make the base
address configurable for consistency and future proof.

Change-Id: I776e43ff2b0408577919b0b72849c3e1e5ce0758
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

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uniphier: make eMMC controller base address configurable

The next SoC supports the same eMMC controller, but the register
base will be changed. Make it configurable.

Change-Id: I00cb5531bc3d8d49357

uniphier: make eMMC controller base address configurable

The next SoC supports the same eMMC controller, but the register
base will be changed. Make it configurable.

Change-Id: I00cb5531bc3d8d49357ad5e922cdd3d785355edf
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

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Merge changes from topic "lm/fconf" into integration

* changes:
arm-io: Panic in case of io setup failure
MISRA fix: Use boolean essential type
fconf: Add documentation
fconf: Move platform

Merge changes from topic "lm/fconf" into integration

* changes:
arm-io: Panic in case of io setup failure
MISRA fix: Use boolean essential type
fconf: Add documentation
fconf: Move platform io policies into fconf
fconf: Add mbedtls shared heap as property
fconf: Add TBBR disable_authentication property
fconf: Add dynamic config DTBs info as property
fconf: Populate properties from dtb during bl2 setup
fconf: Load config dtb from bl1
fconf: initial commit

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Fixes ROTPK hash generation for ECDSA encryption

Forced hash generation used to always generate hash via RSA encryption.
This patch changes encryption based on ARM_ROTPK_LOCATION.
Also removes setti

Fixes ROTPK hash generation for ECDSA encryption

Forced hash generation used to always generate hash via RSA encryption.
This patch changes encryption based on ARM_ROTPK_LOCATION.
Also removes setting KEY_ALG based on ARM_ROTPL_LOCATION - there is no
relation between these two.

Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com>
Change-Id: Id727d2ed06176a243719fd0adfa0cae26c325005

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Merge changes from topic "spmd" into integration

* changes:
SPMD: enable SPM dispatcher support
SPMD: hook SPMD into standard services framework
SPMD: add SPM dispatcher based upon SPCI Beta 0

Merge changes from topic "spmd" into integration

* changes:
SPMD: enable SPM dispatcher support
SPMD: hook SPMD into standard services framework
SPMD: add SPM dispatcher based upon SPCI Beta 0 spec
SPMD: add support to run BL32 in TDRAM and BL31 in secure DRAM on Arm FVP
SPMD: add support for an example SPM core manifest
SPMD: add SPCI Beta 0 specification header file

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Merge "coverity: Fix MISRA null pointer violations" into integration

Merge "fvp: Slightly Bump the stack size for bl1 and bl2" into integration

Merge changes from topic "amlogic/axg" into integration

* changes:
amlogic: axg: Add a build flag when using ATOS as BL32
amlogic: axg: Add support for the A113D (AXG) platform

SPMD: enable SPM dispatcher support

This patch adds support to the build system to include support for the SPM
dispatcher when the SPD configuration option is spmd.

Signed-off-by: Achin Gupta <achi

SPMD: enable SPM dispatcher support

This patch adds support to the build system to include support for the SPM
dispatcher when the SPD configuration option is spmd.

Signed-off-by: Achin Gupta <achin.gupta@arm.com>
Signed-off-by: Artsem Artsemenka <artsem.artsemenka@arm.com>
Change-Id: Ic1ae50ecd7403fcbcf1d318abdbd6ebdc642f732

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SPMD: add support to run BL32 in TDRAM and BL31 in secure DRAM on Arm FVP

This patch reserves and maps the Trusted DRAM for SPM core execution.
It also configures the TrustZone address space control

SPMD: add support to run BL32 in TDRAM and BL31 in secure DRAM on Arm FVP

This patch reserves and maps the Trusted DRAM for SPM core execution.
It also configures the TrustZone address space controller to run BL31
in secure DRAM.

Signed-off-by: Achin Gupta <achin.gupta@arm.com>
Signed-off-by: Artsem Artsemenka <artsem.artsemenka@arm.com>
Change-Id: I7e1bb3bbc61a0fec6a9cb595964ff553620c21dc

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SPMD: add support for an example SPM core manifest

This patch repurposes the TOS FW configuration file as the manifest for
the SPM core component which will reside at the secure EL adjacent to
EL3.

SPMD: add support for an example SPM core manifest

This patch repurposes the TOS FW configuration file as the manifest for
the SPM core component which will reside at the secure EL adjacent to
EL3. The SPM dispatcher component will use the manifest to determine how
the core component must be initialised. Routines and data structure to
parse the manifest have also been added.

Signed-off-by: Achin Gupta <achin.gupta@arm.com>
Signed-off-by: Artsem Artsemenka <artsem.artsemenka@arm.com>
Change-Id: Id94f8ece43b4e05609f0a1d364708a912f6203cb

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Merge changes from topics "rddaniel", "rdn1edge_dual" into integration

* changes:
plat/arm: add board support for rd-daniel platform
plat/arm/sgi: move GIC related constants to board files
pla

Merge changes from topics "rddaniel", "rdn1edge_dual" into integration

* changes:
plat/arm: add board support for rd-daniel platform
plat/arm/sgi: move GIC related constants to board files
platform/arm/sgi: add multi-chip mode parameter in HW_CONFIG dts
board/rdn1edge: add support for dual-chip configuration
drivers/arm/scmi: allow use of multiple SCMI channels
drivers/mhu: derive doorbell base address
plat/arm/sgi: include AFF3 affinity in core position calculation
plat/arm/sgi: add macros for remote chip device region
plat/arm/sgi: add chip_id and multi_chip_mode to platform variant info
plat/arm/sgi: move bl31_platform_setup to board file

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Merge "intel: Include address range check for SiP Mailbox" into integration

Merge "qemu: define ARMV7_SUPPORTS_VFP" into integration

plat/arm: add board support for rd-daniel platform

Add the initial board support for RD-Daniel Config-M platform.

Change-Id: I36df16c745bfe4bc817e275ad4722e5de57733cd
Signed-off-by: Jagadeesh Ujja

plat/arm: add board support for rd-daniel platform

Add the initial board support for RD-Daniel Config-M platform.

Change-Id: I36df16c745bfe4bc817e275ad4722e5de57733cd
Signed-off-by: Jagadeesh Ujja <jagadeesh.ujja@arm.com>
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>

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board/rde1edge: fix incorrect topology tree description

RD-E1-Edge platform consists of two clusters with eight CPUs each and
two processing elements (PE) per CPU. Commit a9fbf13e049e (plat/arm/sgi:

board/rde1edge: fix incorrect topology tree description

RD-E1-Edge platform consists of two clusters with eight CPUs each and
two processing elements (PE) per CPU. Commit a9fbf13e049e (plat/arm/sgi:
move topology information to board folder) defined the RD-E1-Edge
topology tree to have two clusters with eight CPUs each but PE per CPU
entries were not added. This patch fixes the topology tree accordingly.

Change-Id: I7f97f0013be60e5d51c214fce3962e246bae8a0b
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>

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plat/arm/sgi: move GIC related constants to board files

In preparation for adding support for Reference Design platforms
which have different base addresses for GIC Distributor or
Redistributor, mov

plat/arm/sgi: move GIC related constants to board files

In preparation for adding support for Reference Design platforms
which have different base addresses for GIC Distributor or
Redistributor, move GIC related base addresses to individual platform
definition files.

Change-Id: Iecf52b4392a30b86905e1cd047c0ff87d59d0191
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>

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