1 /* 2 * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #ifndef ARM_DEF_H 7 #define ARM_DEF_H 8 9 #include <arch.h> 10 #include <common/interrupt_props.h> 11 #include <common/tbbr/tbbr_img_def.h> 12 #include <drivers/arm/gic_common.h> 13 #include <lib/utils_def.h> 14 #include <lib/xlat_tables/xlat_tables_defs.h> 15 #include <plat/common/common_def.h> 16 17 /****************************************************************************** 18 * Definitions common to all ARM standard platforms 19 *****************************************************************************/ 20 21 /* Special value used to verify platform parameters from BL2 to BL31 */ 22 #define ARM_BL31_PLAT_PARAM_VAL ULL(0x0f1e2d3c4b5a6978) 23 24 #define ARM_SYSTEM_COUNT U(1) 25 26 #define ARM_CACHE_WRITEBACK_SHIFT 6 27 28 /* 29 * Macros mapping the MPIDR Affinity levels to ARM Platform Power levels. The 30 * power levels have a 1:1 mapping with the MPIDR affinity levels. 31 */ 32 #define ARM_PWR_LVL0 MPIDR_AFFLVL0 33 #define ARM_PWR_LVL1 MPIDR_AFFLVL1 34 #define ARM_PWR_LVL2 MPIDR_AFFLVL2 35 #define ARM_PWR_LVL3 MPIDR_AFFLVL3 36 37 /* 38 * Macros for local power states in ARM platforms encoded by State-ID field 39 * within the power-state parameter. 40 */ 41 /* Local power state for power domains in Run state. */ 42 #define ARM_LOCAL_STATE_RUN U(0) 43 /* Local power state for retention. Valid only for CPU power domains */ 44 #define ARM_LOCAL_STATE_RET U(1) 45 /* Local power state for OFF/power-down. Valid for CPU and cluster power 46 domains */ 47 #define ARM_LOCAL_STATE_OFF U(2) 48 49 /* Memory location options for TSP */ 50 #define ARM_TRUSTED_SRAM_ID 0 51 #define ARM_TRUSTED_DRAM_ID 1 52 #define ARM_DRAM_ID 2 53 54 /* The first 4KB of Trusted SRAM are used as shared memory */ 55 #define ARM_TRUSTED_SRAM_BASE UL(0x04000000) 56 #define ARM_SHARED_RAM_BASE ARM_TRUSTED_SRAM_BASE 57 #define ARM_SHARED_RAM_SIZE UL(0x00001000) /* 4 KB */ 58 59 /* The remaining Trusted SRAM is used to load the BL images */ 60 #define ARM_BL_RAM_BASE (ARM_SHARED_RAM_BASE + \ 61 ARM_SHARED_RAM_SIZE) 62 #define ARM_BL_RAM_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 63 ARM_SHARED_RAM_SIZE) 64 65 /* 66 * The top 16MB of DRAM1 is configured as secure access only using the TZC 67 * - SCP TZC DRAM: If present, DRAM reserved for SCP use 68 * - AP TZC DRAM: The remaining TZC secured DRAM reserved for AP use 69 */ 70 #define ARM_TZC_DRAM1_SIZE UL(0x01000000) 71 72 #define ARM_SCP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \ 73 ARM_DRAM1_SIZE - \ 74 ARM_SCP_TZC_DRAM1_SIZE) 75 #define ARM_SCP_TZC_DRAM1_SIZE PLAT_ARM_SCP_TZC_DRAM1_SIZE 76 #define ARM_SCP_TZC_DRAM1_END (ARM_SCP_TZC_DRAM1_BASE + \ 77 ARM_SCP_TZC_DRAM1_SIZE - 1) 78 79 /* 80 * Define a 2MB region within the TZC secured DRAM for use by EL3 runtime 81 * firmware. This region is meant to be NOLOAD and will not be zero 82 * initialized. Data sections with the attribute `arm_el3_tzc_dram` will be 83 * placed here. 84 */ 85 #define ARM_EL3_TZC_DRAM1_BASE (ARM_SCP_TZC_DRAM1_BASE - ARM_EL3_TZC_DRAM1_SIZE) 86 #define ARM_EL3_TZC_DRAM1_SIZE UL(0x00200000) /* 2 MB */ 87 #define ARM_EL3_TZC_DRAM1_END (ARM_EL3_TZC_DRAM1_BASE + \ 88 ARM_EL3_TZC_DRAM1_SIZE - 1) 89 90 #define ARM_AP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \ 91 ARM_DRAM1_SIZE - \ 92 ARM_TZC_DRAM1_SIZE) 93 #define ARM_AP_TZC_DRAM1_SIZE (ARM_TZC_DRAM1_SIZE - \ 94 (ARM_SCP_TZC_DRAM1_SIZE + \ 95 ARM_EL3_TZC_DRAM1_SIZE)) 96 #define ARM_AP_TZC_DRAM1_END (ARM_AP_TZC_DRAM1_BASE + \ 97 ARM_AP_TZC_DRAM1_SIZE - 1) 98 99 /* Define the Access permissions for Secure peripherals to NS_DRAM */ 100 #if ARM_CRYPTOCELL_INTEG 101 /* 102 * Allow Secure peripheral to read NS DRAM when integrated with CryptoCell. 103 * This is required by CryptoCell to authenticate BL33 which is loaded 104 * into the Non Secure DDR. 105 */ 106 #define ARM_TZC_NS_DRAM_S_ACCESS TZC_REGION_S_RD 107 #else 108 #define ARM_TZC_NS_DRAM_S_ACCESS TZC_REGION_S_NONE 109 #endif 110 111 #ifdef SPD_opteed 112 /* 113 * BL2 needs to map 4MB at the end of TZC_DRAM1 in order to 114 * load/authenticate the trusted os extra image. The first 512KB of 115 * TZC_DRAM1 are reserved for trusted os (OPTEE). The extra image loading 116 * for OPTEE is paged image which only include the paging part using 117 * virtual memory but without "init" data. OPTEE will copy the "init" data 118 * (from pager image) to the first 512KB of TZC_DRAM, and then copy the 119 * extra image behind the "init" data. 120 */ 121 #define ARM_OPTEE_PAGEABLE_LOAD_BASE (ARM_AP_TZC_DRAM1_BASE + \ 122 ARM_AP_TZC_DRAM1_SIZE - \ 123 ARM_OPTEE_PAGEABLE_LOAD_SIZE) 124 #define ARM_OPTEE_PAGEABLE_LOAD_SIZE UL(0x400000) 125 #define ARM_OPTEE_PAGEABLE_LOAD_MEM MAP_REGION_FLAT( \ 126 ARM_OPTEE_PAGEABLE_LOAD_BASE, \ 127 ARM_OPTEE_PAGEABLE_LOAD_SIZE, \ 128 MT_MEMORY | MT_RW | MT_SECURE) 129 130 /* 131 * Map the memory for the OP-TEE core (also known as OP-TEE pager when paging 132 * support is enabled). 133 */ 134 #define ARM_MAP_OPTEE_CORE_MEM MAP_REGION_FLAT( \ 135 BL32_BASE, \ 136 BL32_LIMIT - BL32_BASE, \ 137 MT_MEMORY | MT_RW | MT_SECURE) 138 #endif /* SPD_opteed */ 139 140 #define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE 141 #define ARM_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \ 142 ARM_TZC_DRAM1_SIZE) 143 #define ARM_NS_DRAM1_END (ARM_NS_DRAM1_BASE + \ 144 ARM_NS_DRAM1_SIZE - 1) 145 146 #define ARM_DRAM1_BASE ULL(0x80000000) 147 #define ARM_DRAM1_SIZE ULL(0x80000000) 148 #define ARM_DRAM1_END (ARM_DRAM1_BASE + \ 149 ARM_DRAM1_SIZE - 1) 150 151 #define ARM_DRAM2_BASE PLAT_ARM_DRAM2_BASE 152 #define ARM_DRAM2_SIZE PLAT_ARM_DRAM2_SIZE 153 #define ARM_DRAM2_END (ARM_DRAM2_BASE + \ 154 ARM_DRAM2_SIZE - 1) 155 156 #define ARM_IRQ_SEC_PHY_TIMER 29 157 158 #define ARM_IRQ_SEC_SGI_0 8 159 #define ARM_IRQ_SEC_SGI_1 9 160 #define ARM_IRQ_SEC_SGI_2 10 161 #define ARM_IRQ_SEC_SGI_3 11 162 #define ARM_IRQ_SEC_SGI_4 12 163 #define ARM_IRQ_SEC_SGI_5 13 164 #define ARM_IRQ_SEC_SGI_6 14 165 #define ARM_IRQ_SEC_SGI_7 15 166 167 /* 168 * Define a list of Group 1 Secure and Group 0 interrupt properties as per GICv3 169 * terminology. On a GICv2 system or mode, the lists will be merged and treated 170 * as Group 0 interrupts. 171 */ 172 #define ARM_G1S_IRQ_PROPS(grp) \ 173 INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 174 GIC_INTR_CFG_LEVEL), \ 175 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 176 GIC_INTR_CFG_EDGE), \ 177 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 178 GIC_INTR_CFG_EDGE), \ 179 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 180 GIC_INTR_CFG_EDGE), \ 181 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 182 GIC_INTR_CFG_EDGE), \ 183 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 184 GIC_INTR_CFG_EDGE), \ 185 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 186 GIC_INTR_CFG_EDGE) 187 188 #define ARM_G0_IRQ_PROPS(grp) \ 189 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, PLAT_SDEI_NORMAL_PRI, (grp), \ 190 GIC_INTR_CFG_EDGE), \ 191 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 192 GIC_INTR_CFG_EDGE) 193 194 #define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \ 195 ARM_SHARED_RAM_BASE, \ 196 ARM_SHARED_RAM_SIZE, \ 197 MT_DEVICE | MT_RW | MT_SECURE) 198 199 #define ARM_MAP_NS_DRAM1 MAP_REGION_FLAT( \ 200 ARM_NS_DRAM1_BASE, \ 201 ARM_NS_DRAM1_SIZE, \ 202 MT_MEMORY | MT_RW | MT_NS) 203 204 #define ARM_MAP_DRAM2 MAP_REGION_FLAT( \ 205 ARM_DRAM2_BASE, \ 206 ARM_DRAM2_SIZE, \ 207 MT_MEMORY | MT_RW | MT_NS) 208 209 #define ARM_MAP_TSP_SEC_MEM MAP_REGION_FLAT( \ 210 TSP_SEC_MEM_BASE, \ 211 TSP_SEC_MEM_SIZE, \ 212 MT_MEMORY | MT_RW | MT_SECURE) 213 214 #if ARM_BL31_IN_DRAM 215 #define ARM_MAP_BL31_SEC_DRAM MAP_REGION_FLAT( \ 216 BL31_BASE, \ 217 PLAT_ARM_MAX_BL31_SIZE, \ 218 MT_MEMORY | MT_RW | MT_SECURE) 219 #endif 220 221 #define ARM_MAP_EL3_TZC_DRAM MAP_REGION_FLAT( \ 222 ARM_EL3_TZC_DRAM1_BASE, \ 223 ARM_EL3_TZC_DRAM1_SIZE, \ 224 MT_MEMORY | MT_RW | MT_SECURE) 225 226 #if defined(SPD_spmd) 227 #define ARM_MAP_TRUSTED_DRAM MAP_REGION_FLAT( \ 228 PLAT_ARM_TRUSTED_DRAM_BASE, \ 229 PLAT_ARM_TRUSTED_DRAM_SIZE, \ 230 MT_MEMORY | MT_RW | MT_SECURE) 231 #endif 232 233 234 /* 235 * Mapping for the BL1 RW region. This mapping is needed by BL2 in order to 236 * share the Mbed TLS heap. Since the heap is allocated inside BL1, it resides 237 * in the BL1 RW region. Hence, BL2 needs access to the BL1 RW region in order 238 * to be able to access the heap. 239 */ 240 #define ARM_MAP_BL1_RW MAP_REGION_FLAT( \ 241 BL1_RW_BASE, \ 242 BL1_RW_LIMIT - BL1_RW_BASE, \ 243 MT_MEMORY | MT_RW | MT_SECURE) 244 245 /* 246 * If SEPARATE_CODE_AND_RODATA=1 we define a region for each section 247 * otherwise one region is defined containing both. 248 */ 249 #if SEPARATE_CODE_AND_RODATA 250 #define ARM_MAP_BL_RO MAP_REGION_FLAT( \ 251 BL_CODE_BASE, \ 252 BL_CODE_END - BL_CODE_BASE, \ 253 MT_CODE | MT_SECURE), \ 254 MAP_REGION_FLAT( \ 255 BL_RO_DATA_BASE, \ 256 BL_RO_DATA_END \ 257 - BL_RO_DATA_BASE, \ 258 MT_RO_DATA | MT_SECURE) 259 #else 260 #define ARM_MAP_BL_RO MAP_REGION_FLAT( \ 261 BL_CODE_BASE, \ 262 BL_CODE_END - BL_CODE_BASE, \ 263 MT_CODE | MT_SECURE) 264 #endif 265 #if USE_COHERENT_MEM 266 #define ARM_MAP_BL_COHERENT_RAM MAP_REGION_FLAT( \ 267 BL_COHERENT_RAM_BASE, \ 268 BL_COHERENT_RAM_END \ 269 - BL_COHERENT_RAM_BASE, \ 270 MT_DEVICE | MT_RW | MT_SECURE) 271 #endif 272 #if USE_ROMLIB 273 #define ARM_MAP_ROMLIB_CODE MAP_REGION_FLAT( \ 274 ROMLIB_RO_BASE, \ 275 ROMLIB_RO_LIMIT - ROMLIB_RO_BASE,\ 276 MT_CODE | MT_SECURE) 277 278 #define ARM_MAP_ROMLIB_DATA MAP_REGION_FLAT( \ 279 ROMLIB_RW_BASE, \ 280 ROMLIB_RW_END - ROMLIB_RW_BASE,\ 281 MT_MEMORY | MT_RW | MT_SECURE) 282 #endif 283 284 /* 285 * Map mem_protect flash region with read and write permissions 286 */ 287 #define ARM_V2M_MAP_MEM_PROTECT MAP_REGION_FLAT(PLAT_ARM_MEM_PROT_ADDR, \ 288 V2M_FLASH_BLOCK_SIZE, \ 289 MT_DEVICE | MT_RW | MT_SECURE) 290 291 /* 292 * The max number of regions like RO(code), coherent and data required by 293 * different BL stages which need to be mapped in the MMU. 294 */ 295 #define ARM_BL_REGIONS 5 296 297 #define MAX_MMAP_REGIONS (PLAT_ARM_MMAP_ENTRIES + \ 298 ARM_BL_REGIONS) 299 300 /* Memory mapped Generic timer interfaces */ 301 #define ARM_SYS_CNTCTL_BASE UL(0x2a430000) 302 #define ARM_SYS_CNTREAD_BASE UL(0x2a800000) 303 #define ARM_SYS_TIMCTL_BASE UL(0x2a810000) 304 #define ARM_SYS_CNT_BASE_S UL(0x2a820000) 305 #define ARM_SYS_CNT_BASE_NS UL(0x2a830000) 306 307 #define ARM_CONSOLE_BAUDRATE 115200 308 309 /* Trusted Watchdog constants */ 310 #define ARM_SP805_TWDG_BASE UL(0x2a490000) 311 #define ARM_SP805_TWDG_CLK_HZ 32768 312 /* The TBBR document specifies a watchdog timeout of 256 seconds. SP805 313 * asserts reset after two consecutive countdowns (2 x 128 = 256 sec) */ 314 #define ARM_TWDG_TIMEOUT_SEC 128 315 #define ARM_TWDG_LOAD_VAL (ARM_SP805_TWDG_CLK_HZ * \ 316 ARM_TWDG_TIMEOUT_SEC) 317 318 /****************************************************************************** 319 * Required platform porting definitions common to all ARM standard platforms 320 *****************************************************************************/ 321 322 /* 323 * This macro defines the deepest retention state possible. A higher state 324 * id will represent an invalid or a power down state. 325 */ 326 #define PLAT_MAX_RET_STATE ARM_LOCAL_STATE_RET 327 328 /* 329 * This macro defines the deepest power down states possible. Any state ID 330 * higher than this is invalid. 331 */ 332 #define PLAT_MAX_OFF_STATE ARM_LOCAL_STATE_OFF 333 334 /* 335 * Some data must be aligned on the biggest cache line size in the platform. 336 * This is known only to the platform as it might have a combination of 337 * integrated and external caches. 338 */ 339 #define CACHE_WRITEBACK_GRANULE (U(1) << ARM_CACHE_WRITEBACK_SHIFT) 340 341 /* 342 * To enable TB_FW_CONFIG to be loaded by BL1, define the corresponding base 343 * and limit. Leave enough space of BL2 meminfo. 344 */ 345 #define ARM_TB_FW_CONFIG_BASE (ARM_BL_RAM_BASE + sizeof(meminfo_t)) 346 #define ARM_TB_FW_CONFIG_LIMIT (ARM_BL_RAM_BASE + (PAGE_SIZE / 2U)) 347 348 /* 349 * Boot parameters passed from BL2 to BL31/BL32 are stored here 350 */ 351 #define ARM_BL2_MEM_DESC_BASE ARM_TB_FW_CONFIG_LIMIT 352 #define ARM_BL2_MEM_DESC_LIMIT (ARM_BL2_MEM_DESC_BASE + \ 353 (PAGE_SIZE / 2U)) 354 355 /* 356 * Define limit of firmware configuration memory: 357 * ARM_TB_FW_CONFIG + ARM_BL2_MEM_DESC memory 358 */ 359 #define ARM_FW_CONFIG_LIMIT (ARM_BL_RAM_BASE + PAGE_SIZE) 360 361 /******************************************************************************* 362 * BL1 specific defines. 363 * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of 364 * addresses. 365 ******************************************************************************/ 366 #define BL1_RO_BASE PLAT_ARM_TRUSTED_ROM_BASE 367 #define BL1_RO_LIMIT (PLAT_ARM_TRUSTED_ROM_BASE \ 368 + (PLAT_ARM_TRUSTED_ROM_SIZE - \ 369 PLAT_ARM_MAX_ROMLIB_RO_SIZE)) 370 /* 371 * Put BL1 RW at the top of the Trusted SRAM. 372 */ 373 #define BL1_RW_BASE (ARM_BL_RAM_BASE + \ 374 ARM_BL_RAM_SIZE - \ 375 (PLAT_ARM_MAX_BL1_RW_SIZE +\ 376 PLAT_ARM_MAX_ROMLIB_RW_SIZE)) 377 #define BL1_RW_LIMIT (ARM_BL_RAM_BASE + \ 378 (ARM_BL_RAM_SIZE - PLAT_ARM_MAX_ROMLIB_RW_SIZE)) 379 380 #define ROMLIB_RO_BASE BL1_RO_LIMIT 381 #define ROMLIB_RO_LIMIT (PLAT_ARM_TRUSTED_ROM_BASE + PLAT_ARM_TRUSTED_ROM_SIZE) 382 383 #define ROMLIB_RW_BASE (BL1_RW_BASE + PLAT_ARM_MAX_BL1_RW_SIZE) 384 #define ROMLIB_RW_END (ROMLIB_RW_BASE + PLAT_ARM_MAX_ROMLIB_RW_SIZE) 385 386 /******************************************************************************* 387 * BL2 specific defines. 388 ******************************************************************************/ 389 #if BL2_AT_EL3 390 /* Put BL2 towards the middle of the Trusted SRAM */ 391 #define BL2_BASE (ARM_TRUSTED_SRAM_BASE + \ 392 (PLAT_ARM_TRUSTED_SRAM_SIZE >> 1) + 0x2000) 393 #define BL2_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) 394 395 #else 396 /* 397 * Put BL2 just below BL1. 398 */ 399 #define BL2_BASE (BL1_RW_BASE - PLAT_ARM_MAX_BL2_SIZE) 400 #define BL2_LIMIT BL1_RW_BASE 401 #endif 402 403 /******************************************************************************* 404 * BL31 specific defines. 405 ******************************************************************************/ 406 #if ARM_BL31_IN_DRAM || SEPARATE_NOBITS_REGION 407 /* 408 * Put BL31 at the bottom of TZC secured DRAM 409 */ 410 #define BL31_BASE ARM_AP_TZC_DRAM1_BASE 411 #define BL31_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ 412 PLAT_ARM_MAX_BL31_SIZE) 413 /* 414 * For SEPARATE_NOBITS_REGION, BL31 PROGBITS are loaded in TZC secured DRAM. 415 * And BL31 NOBITS are loaded in Trusted SRAM such that BL2 is overwritten. 416 */ 417 #if SEPARATE_NOBITS_REGION 418 #define BL31_NOBITS_BASE BL2_BASE 419 #define BL31_NOBITS_LIMIT BL2_LIMIT 420 #endif /* SEPARATE_NOBITS_REGION */ 421 #elif (RESET_TO_BL31) 422 /* Ensure Position Independent support (PIE) is enabled for this config.*/ 423 # if !ENABLE_PIE 424 # error "BL31 must be a PIE if RESET_TO_BL31=1." 425 #endif 426 /* 427 * Since this is PIE, we can define BL31_BASE to 0x0 since this macro is solely 428 * used for building BL31 and not used for loading BL31. 429 */ 430 # define BL31_BASE 0x0 431 # define BL31_LIMIT PLAT_ARM_MAX_BL31_SIZE 432 #else 433 /* Put BL31 below BL2 in the Trusted SRAM.*/ 434 #define BL31_BASE ((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)\ 435 - PLAT_ARM_MAX_BL31_SIZE) 436 #define BL31_PROGBITS_LIMIT BL2_BASE 437 /* 438 * For BL2_AT_EL3 make sure the BL31 can grow up until BL2_BASE. This is 439 * because in the BL2_AT_EL3 configuration, BL2 is always resident. 440 */ 441 #if BL2_AT_EL3 442 #define BL31_LIMIT BL2_BASE 443 #else 444 #define BL31_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) 445 #endif 446 #endif 447 448 #if !defined(__aarch64__) || JUNO_AARCH32_EL3_RUNTIME 449 /******************************************************************************* 450 * BL32 specific defines for EL3 runtime in AArch32 mode 451 ******************************************************************************/ 452 # if RESET_TO_SP_MIN && !JUNO_AARCH32_EL3_RUNTIME 453 /* 454 * SP_MIN is the only BL image in SRAM. Allocate the whole of SRAM (excluding 455 * the page reserved for fw_configs) to BL32 456 */ 457 # define BL32_BASE ARM_FW_CONFIG_LIMIT 458 # define BL32_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) 459 # else 460 /* Put BL32 below BL2 in the Trusted SRAM.*/ 461 # define BL32_BASE ((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)\ 462 - PLAT_ARM_MAX_BL32_SIZE) 463 # define BL32_PROGBITS_LIMIT BL2_BASE 464 # define BL32_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) 465 # endif /* RESET_TO_SP_MIN && !JUNO_AARCH32_EL3_RUNTIME */ 466 467 #else 468 /******************************************************************************* 469 * BL32 specific defines for EL3 runtime in AArch64 mode 470 ******************************************************************************/ 471 /* 472 * On ARM standard platforms, the TSP can execute from Trusted SRAM, 473 * Trusted DRAM (if available) or the DRAM region secured by the TrustZone 474 * controller. 475 */ 476 # if SPM_MM 477 # define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000)) 478 # define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - ULL(0x200000)) 479 # define BL32_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000)) 480 # define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ 481 ARM_AP_TZC_DRAM1_SIZE) 482 # elif defined(SPD_spmd) 483 # define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000)) 484 # define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - ULL(0x200000)) 485 # define BL32_BASE PLAT_ARM_TRUSTED_DRAM_BASE 486 # define BL32_LIMIT (PLAT_ARM_TRUSTED_DRAM_BASE \ 487 + (UL(1) << 21)) 488 # elif ARM_BL31_IN_DRAM 489 # define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + \ 490 PLAT_ARM_MAX_BL31_SIZE) 491 # define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - \ 492 PLAT_ARM_MAX_BL31_SIZE) 493 # define BL32_BASE (ARM_AP_TZC_DRAM1_BASE + \ 494 PLAT_ARM_MAX_BL31_SIZE) 495 # define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ 496 ARM_AP_TZC_DRAM1_SIZE) 497 # elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_SRAM_ID 498 # define TSP_SEC_MEM_BASE ARM_BL_RAM_BASE 499 # define TSP_SEC_MEM_SIZE ARM_BL_RAM_SIZE 500 # define TSP_PROGBITS_LIMIT BL31_BASE 501 # define BL32_BASE ARM_FW_CONFIG_LIMIT 502 # define BL32_LIMIT BL31_BASE 503 # elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_DRAM_ID 504 # define TSP_SEC_MEM_BASE PLAT_ARM_TRUSTED_DRAM_BASE 505 # define TSP_SEC_MEM_SIZE PLAT_ARM_TRUSTED_DRAM_SIZE 506 # define BL32_BASE PLAT_ARM_TRUSTED_DRAM_BASE 507 # define BL32_LIMIT (PLAT_ARM_TRUSTED_DRAM_BASE \ 508 + (UL(1) << 21)) 509 # elif ARM_TSP_RAM_LOCATION_ID == ARM_DRAM_ID 510 # define TSP_SEC_MEM_BASE ARM_AP_TZC_DRAM1_BASE 511 # define TSP_SEC_MEM_SIZE ARM_AP_TZC_DRAM1_SIZE 512 # define BL32_BASE ARM_AP_TZC_DRAM1_BASE 513 # define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ 514 ARM_AP_TZC_DRAM1_SIZE) 515 # else 516 # error "Unsupported ARM_TSP_RAM_LOCATION_ID value" 517 # endif 518 #endif /* !__aarch64__ || JUNO_AARCH32_EL3_RUNTIME */ 519 520 /* 521 * BL32 is mandatory in AArch32. In AArch64, undefine BL32_BASE if there is no 522 * SPD and no SPM-MM, as they are the only ones that can be used as BL32. 523 */ 524 #if defined(__aarch64__) && !JUNO_AARCH32_EL3_RUNTIME 525 # if defined(SPD_none) && !SPM_MM 526 # undef BL32_BASE 527 # endif /* defined(SPD_none) && !SPM_MM */ 528 #endif /* defined(__aarch64__) && !JUNO_AARCH32_EL3_RUNTIME */ 529 530 /******************************************************************************* 531 * FWU Images: NS_BL1U, BL2U & NS_BL2U defines. 532 ******************************************************************************/ 533 #define BL2U_BASE BL2_BASE 534 #define BL2U_LIMIT BL2_LIMIT 535 536 #define NS_BL2U_BASE ARM_NS_DRAM1_BASE 537 #define NS_BL1U_BASE (PLAT_ARM_NVM_BASE + UL(0x03EB8000)) 538 539 /* 540 * ID of the secure physical generic timer interrupt used by the TSP. 541 */ 542 #define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER 543 544 545 /* 546 * One cache line needed for bakery locks on ARM platforms 547 */ 548 #define PLAT_PERCPU_BAKERY_LOCK_SIZE (1 * CACHE_WRITEBACK_GRANULE) 549 550 /* Priority levels for ARM platforms */ 551 #define PLAT_RAS_PRI 0x10 552 #define PLAT_SDEI_CRITICAL_PRI 0x60 553 #define PLAT_SDEI_NORMAL_PRI 0x70 554 555 /* ARM platforms use 3 upper bits of secure interrupt priority */ 556 #define ARM_PRI_BITS 3 557 558 /* SGI used for SDEI signalling */ 559 #define ARM_SDEI_SGI ARM_IRQ_SEC_SGI_0 560 561 /* ARM SDEI dynamic private event numbers */ 562 #define ARM_SDEI_DP_EVENT_0 1000 563 #define ARM_SDEI_DP_EVENT_1 1001 564 #define ARM_SDEI_DP_EVENT_2 1002 565 566 /* ARM SDEI dynamic shared event numbers */ 567 #define ARM_SDEI_DS_EVENT_0 2000 568 #define ARM_SDEI_DS_EVENT_1 2001 569 #define ARM_SDEI_DS_EVENT_2 2002 570 571 #define ARM_SDEI_PRIVATE_EVENTS \ 572 SDEI_DEFINE_EVENT_0(ARM_SDEI_SGI), \ 573 SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_0, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ 574 SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_1, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ 575 SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_2, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC) 576 577 #define ARM_SDEI_SHARED_EVENTS \ 578 SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_0, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ 579 SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_1, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ 580 SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_2, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC) 581 582 #endif /* ARM_DEF_H */ 583