rcar_gen3: plat: Update IPL and Secure Monitor Rev.2.0.6

Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> # upstream updat

rcar_gen3: plat: Update IPL and Secure Monitor Rev.2.0.6

Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> # upstream update
Change-Id: I70c3d873b1d05075257034aee5e19c754be911e0

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rcar_gen3: plat: Update IPL and Secure Monitor Rev.2.0.5

Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Sig

rcar_gen3: plat: Update IPL and Secure Monitor Rev.2.0.5

Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> # upstream update
Change-Id: I8ef32a67f7984d8bcfcc3655988b559efa6e65ab

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rcar_gen3: plat: Change fixed destination address of BL31 and BL32

This patch changes the destination address of BL31 and BL32 From
fixed address for getting from the each certificates.

Signed-off-

rcar_gen3: plat: Change fixed destination address of BL31 and BL32

This patch changes the destination address of BL31 and BL32 From
fixed address for getting from the each certificates.

Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> # upstream rework
Change-Id: Ide11776feff25e6fdd55ab28503a15b658b2e0d5

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Merge "fconf: Move remaining arm platform to fconf" into integration

Merge changes from topic "uniphier" into integration

* changes:
uniphier: make I/O register region configurable
uniphier: make PSCI related base address configurable
uniphier: make counter con

Merge changes from topic "uniphier" into integration

* changes:
uniphier: make I/O register region configurable
uniphier: make PSCI related base address configurable
uniphier: make counter control base address configurable
uniphier: make UART base address configurable
uniphier: make pinmon base address configurable
uniphier: make NAND controller base address configurable
uniphier: make eMMC controller base address configurable

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mediatek: mt8183: protect 4GB~8GB dram memory

The offset there is the virtual address space on the bus side (1-9GB for 8GB RAM),
and that emi_mpu_set_region_protection will translate to the physical

mediatek: mt8183: protect 4GB~8GB dram memory

The offset there is the virtual address space on the bus side (1-9GB for 8GB RAM),
and that emi_mpu_set_region_protection will translate to the physical memory space (0-8GB).

8GB is 33-bit (the memory bus width is 33-bit on this platform),
so 0x23FFFFFFFUL-EMI_PHY_OFFSET = 0x1_FFFF_FFFF.

Change-Id: I7be4759ed7546f7e15a5868b6f08988928c34075
Signed-off-by: Xi Chen <xixi.chen@mediatek.com>

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corstone700: adding support for stack protector for the FVP

Adding support for generating a semi-random number required for
enabling building TF-A with stack protector support.
TF-A for corstone-700

corstone700: adding support for stack protector for the FVP

Adding support for generating a semi-random number required for
enabling building TF-A with stack protector support.
TF-A for corstone-700 may now be built using ENABLE_STACK_PROTECTOR=all

Change-Id: I03e1be1a8d4e4a822cf286f3b9ad4da4337ca765
Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>

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Merge changes from topic "uniphier" into integration

* changes:
uniphier: extend boot device detection for future SoCs
uniphier: change block_addressing flag to bool
uniphier: change the retur

Merge changes from topic "uniphier" into integration

* changes:
uniphier: extend boot device detection for future SoCs
uniphier: change block_addressing flag to bool
uniphier: change the return value type of .is_usb_boot() to bool

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allwinner: Implement PSCI system suspend using SCPI

If an SCP firmware is present and able to communicate via SCPI, then use
that to implement CPU and system power state transitions, including CPU
h

allwinner: Implement PSCI system suspend using SCPI

If an SCP firmware is present and able to communicate via SCPI, then use
that to implement CPU and system power state transitions, including CPU
hotplug and system suspend. Otherwise, fall back to the existing CPU
power control implementation.

The last 16 KiB of SRAM A2 are reserved for the SCP firmware, and the
SCPI shared memory is at the very end of this region (and therefore the
end of SRAM A2). BL31 continues to start at the beginning of SRAM A2
(not counting the ARISC exception vector area) and fills up to the
beginning of the SCP firmware.

Because the SCP firmware is not loaded adjacent to the ARISC exception
vector area, the jump instructions used for exception handling cannot be
included in the SCP firmware image, and must be initialized here before
turning on the SCP.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: I37b9b9636f94d4125230423726f3ac5e9cdb551c

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allwinner: Add a msgbox driver for use with SCPI

The function names follow the naming convention used by the existing
ARM SCPI client.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id:

allwinner: Add a msgbox driver for use with SCPI

The function names follow the naming convention used by the existing
ARM SCPI client.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: I543bae7d46e206eb405dbedfcf7aeba88a12ca48

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allwinner: Reserve and map space for the SCP firmware

The SCP firmware is allocated the last 16KiB of SRAM A2. This includes
the SCPI shared memory area, which must be mapped as MT_DEVICE to
prevent

allwinner: Reserve and map space for the SCP firmware

The SCP firmware is allocated the last 16KiB of SRAM A2. This includes
the SCPI shared memory area, which must be mapped as MT_DEVICE to
prevent problems with cache coherency between the AP CPUs and the SCP.
For simplicity, map the whole SCP region as MT_DEVICE.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Ie39eb5ff281b8898a3c1d9748dc08755f528e2f8

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allwinner: Adjust SRAM A2 base to include the ARISC vectors

The ARISC vector area consists of 0x4000 bytes before the beginning of
usable SRAM. Still, it is technically a part of SRAM A2, so include

allwinner: Adjust SRAM A2 base to include the ARISC vectors

The ARISC vector area consists of 0x4000 bytes before the beginning of
usable SRAM. Still, it is technically a part of SRAM A2, so include it
in the memory definition. This avoids the confusing practice of
subtracting from the beginning of the SRAM region when referencing the
ARISC vectors.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Iae89e01aeab93560159562692e03e88306e2a1bf

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Merge "intel: Change boot source selection" into integration

Merge changes Ib68092d1,I816ea14e into integration

* changes:
plat: marvell: armada: scp_bl2: allow loading up to 8 images
plat: marvell: armada: add support for loading MG CM3 images

fconf: Move remaining arm platform to fconf

Change-Id: I011256ca60672a00b711c3f5725211be64bbc2b2
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>

Merge "Fixes ROTPK hash generation for ECDSA encryption" into integration

plat: imx8m: Fix the rdc memory region slot's offset

Each memory region slot occupies 16bypte space, so
correct the the offset of config register address.

Change-Id: Ief8f21bb8ada78b5663768ee1e40f9

plat: imx8m: Fix the rdc memory region slot's offset

Each memory region slot occupies 16bypte space, so
correct the the offset of config register address.

Change-Id: Ief8f21bb8ada78b5663768ee1e40f9e0eae57165
Signed-off-by: Jacky Bai <ping.bai@nxp.com>

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uniphier: make on-chip SRAM region configurable

The on-chip SRAM region will be changed in the next SoC. Make it
configurable. Also, split the mmap code into a new helper function
so that it can be

uniphier: make on-chip SRAM region configurable

The on-chip SRAM region will be changed in the next SoC. Make it
configurable. Also, split the mmap code into a new helper function
so that it can be re-used for another boot mode.

Change-Id: I89f40432bf852a58ebc9be5d9dec4136b8dc010b
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

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uniphier: make I/O register region configurable

The I/O register region will be changed in the next SoC. Make it
configurable.

Change-Id: Iec0cbd1ef2d0703ebc7c3d3082edd73791bbfec9
Signed-off-by: Ma

uniphier: make I/O register region configurable

The I/O register region will be changed in the next SoC. Make it
configurable.

Change-Id: Iec0cbd1ef2d0703ebc7c3d3082edd73791bbfec9
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

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uniphier: extend boot device detection for future SoCs

The next SoC will have:
- No boot swap
- SD boot
- No USB boot

Add new fields to handle this.

Change-Id: I772395f2c5dfc612e575b0cbd0657

uniphier: extend boot device detection for future SoCs

The next SoC will have:
- No boot swap
- SD boot
- No USB boot

Add new fields to handle this.

Change-Id: I772395f2c5dfc612e575b0cbd0657a5fa9611c25
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

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uniphier: make PSCI related base address configurable

The register base address will be changed in the next SoC. Make it
configurable.

Change-Id: Ibe07bd9db128b0f7e629916cb6ae21ba7984eca9
Signed-of

uniphier: make PSCI related base address configurable

The register base address will be changed in the next SoC. Make it
configurable.

Change-Id: Ibe07bd9db128b0f7e629916cb6ae21ba7984eca9
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

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uniphier: change block_addressing flag to bool

The flag, uniphier_emmc_block_addressing, is boolean logic, so
"bool' is more suitable.

uniphier_emmc_is_over_2gb() is not boolean - it returns 1 / 0

uniphier: change block_addressing flag to bool

The flag, uniphier_emmc_block_addressing, is boolean logic, so
"bool' is more suitable.

uniphier_emmc_is_over_2gb() is not boolean - it returns 1 / 0
depending on the card density, or a negative value on failure.
Rename it to make it less confusing.

Change-Id: Ia646b1929147b644e0df07c46b54ab80548bc3bd
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

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uniphier: make counter control base address configurable

The register base will be changed in the next SoC. Make it
configurable.

Change-Id: I4a7cf85fe50e4d71db58a3372a71774e43193bd3
Signed-off-by:

uniphier: make counter control base address configurable

The register base will be changed in the next SoC. Make it
configurable.

Change-Id: I4a7cf85fe50e4d71db58a3372a71774e43193bd3
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

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uniphier: change the return value type of .is_usb_boot() to bool

This is boolean logic, so "bool" is more suitable.

Change-Id: I439c5099770600a65b8f58390a4c621c2ee487a5
Signed-off-by: Masahiro Yama

uniphier: change the return value type of .is_usb_boot() to bool

This is boolean logic, so "bool" is more suitable.

Change-Id: I439c5099770600a65b8f58390a4c621c2ee487a5
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

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uniphier: make UART base address configurable

The next SoC supports the same UART, but the register base will be
changed. Make it configurable.

Change-Id: Ida5c9151b2f3554afd15555b22838437eef443f7

uniphier: make UART base address configurable

The next SoC supports the same UART, but the register base will be
changed. Make it configurable.

Change-Id: Ida5c9151b2f3554afd15555b22838437eef443f7
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

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