1 /* 2 * Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2019-2020, Intel Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <arch.h> 9 #include <arch_helpers.h> 10 #include <common/bl_common.h> 11 #include <common/debug.h> 12 #include <common/desc_image_load.h> 13 #include <drivers/generic_delay_timer.h> 14 #include <drivers/synopsys/dw_mmc.h> 15 #include <drivers/ti/uart/uart_16550.h> 16 #include <lib/xlat_tables/xlat_tables.h> 17 18 #include "agilex_clock_manager.h" 19 #include "agilex_memory_controller.h" 20 #include "agilex_pinmux.h" 21 #include "ccu/ncore_ccu.h" 22 #include "qspi/cadence_qspi.h" 23 #include "socfpga_emac.h" 24 #include "socfpga_handoff.h" 25 #include "socfpga_mailbox.h" 26 #include "socfpga_private.h" 27 #include "socfpga_reset_manager.h" 28 #include "socfpga_system_manager.h" 29 #include "wdt/watchdog.h" 30 31 32 const mmap_region_t agilex_plat_mmap[] = { 33 MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE, 34 MT_MEMORY | MT_RW | MT_NS), 35 MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE, 36 MT_DEVICE | MT_RW | MT_NS), 37 MAP_REGION_FLAT(DEVICE2_BASE, DEVICE2_SIZE, 38 MT_DEVICE | MT_RW | MT_SECURE), 39 MAP_REGION_FLAT(OCRAM_BASE, OCRAM_SIZE, 40 MT_NON_CACHEABLE | MT_RW | MT_SECURE), 41 MAP_REGION_FLAT(DEVICE3_BASE, DEVICE3_SIZE, 42 MT_DEVICE | MT_RW | MT_SECURE), 43 MAP_REGION_FLAT(MEM64_BASE, MEM64_SIZE, 44 MT_DEVICE | MT_RW | MT_NS), 45 MAP_REGION_FLAT(DEVICE4_BASE, DEVICE4_SIZE, 46 MT_DEVICE | MT_RW | MT_NS), 47 {0}, 48 }; 49 50 boot_source_type boot_source = BOOT_SOURCE; 51 52 void bl2_el3_early_platform_setup(u_register_t x0, u_register_t x1, 53 u_register_t x2, u_register_t x4) 54 { 55 static console_t console; 56 handoff reverse_handoff_ptr; 57 58 generic_delay_timer_init(); 59 60 if (socfpga_get_handoff(&reverse_handoff_ptr)) 61 return; 62 config_pinmux(&reverse_handoff_ptr); 63 config_clkmgr_handoff(&reverse_handoff_ptr); 64 65 enable_nonsecure_access(); 66 deassert_peripheral_reset(); 67 config_hps_hs_before_warm_reset(); 68 69 watchdog_init(get_wdt_clk()); 70 71 console_16550_register(PLAT_UART0_BASE, get_uart_clk(), PLAT_BAUDRATE, 72 &console); 73 74 socfpga_delay_timer_init(); 75 init_ncore_ccu(); 76 socfpga_emac_init(); 77 init_hard_memory_controller(); 78 mailbox_init(); 79 80 if (!intel_mailbox_is_fpga_not_ready()) 81 socfpga_bridges_enable(); 82 } 83 84 85 void bl2_el3_plat_arch_setup(void) 86 { 87 88 struct mmc_device_info info; 89 const mmap_region_t bl_regions[] = { 90 MAP_REGION_FLAT(BL2_BASE, BL2_END - BL2_BASE, 91 MT_MEMORY | MT_RW | MT_SECURE), 92 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, 93 MT_CODE | MT_SECURE), 94 MAP_REGION_FLAT(BL_RO_DATA_BASE, 95 BL_RO_DATA_END - BL_RO_DATA_BASE, 96 MT_RO_DATA | MT_SECURE), 97 #if USE_COHERENT_MEM_BAR 98 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, 99 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, 100 MT_DEVICE | MT_RW | MT_SECURE), 101 #endif 102 {0}, 103 }; 104 105 setup_page_tables(bl_regions, agilex_plat_mmap); 106 107 enable_mmu_el3(0); 108 109 dw_mmc_params_t params = EMMC_INIT_PARAMS(0x100000, get_mmc_clk()); 110 111 info.mmc_dev_type = MMC_IS_SD; 112 info.ocr_voltage = OCR_3_3_3_4 | OCR_3_2_3_3; 113 114 switch (boot_source) { 115 case BOOT_SOURCE_SDMMC: 116 dw_mmc_init(¶ms, &info); 117 socfpga_io_setup(boot_source); 118 break; 119 120 case BOOT_SOURCE_QSPI: 121 mailbox_set_qspi_open(); 122 mailbox_set_qspi_direct(); 123 cad_qspi_init(0, QSPI_CONFIG_CPHA, QSPI_CONFIG_CPOL, 124 QSPI_CONFIG_CSDA, QSPI_CONFIG_CSDADS, 125 QSPI_CONFIG_CSEOT, QSPI_CONFIG_CSSOT, 0); 126 socfpga_io_setup(boot_source); 127 break; 128 129 default: 130 ERROR("Unsupported boot source\n"); 131 panic(); 132 break; 133 } 134 } 135 136 uint32_t get_spsr_for_bl33_entry(void) 137 { 138 unsigned long el_status; 139 unsigned int mode; 140 uint32_t spsr; 141 142 /* Figure out what mode we enter the non-secure world in */ 143 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; 144 el_status &= ID_AA64PFR0_ELX_MASK; 145 146 mode = (el_status) ? MODE_EL2 : MODE_EL1; 147 148 /* 149 * TODO: Consider the possibility of specifying the SPSR in 150 * the FIP ToC and allowing the platform to have a say as 151 * well. 152 */ 153 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 154 return spsr; 155 } 156 157 158 int bl2_plat_handle_post_image_load(unsigned int image_id) 159 { 160 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); 161 162 switch (image_id) { 163 case BL33_IMAGE_ID: 164 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr(); 165 bl_mem_params->ep_info.spsr = get_spsr_for_bl33_entry(); 166 break; 167 default: 168 break; 169 } 170 171 return 0; 172 } 173 174 /******************************************************************************* 175 * Perform any BL3-1 platform setup code 176 ******************************************************************************/ 177 void bl2_platform_setup(void) 178 { 179 } 180 181